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Searched refs:IsSubVecPartReg (Results 1 – 2 of 2) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1603 bool IsSubVecPartReg = SubVecLMUL == RISCVII::VLMUL::LMUL_F2 || in Select() local
1606 (void)IsSubVecPartReg; // Silence unused variable warning without asserts. in Select()
1607 assert((!IsSubVecPartReg || V.isUndef()) && in Select()
H A DRISCVISelLowering.cpp5493 bool IsSubVecPartReg = SubVecLMUL == RISCVII::VLMUL::LMUL_F2 || in lowerINSERT_SUBVECTOR() local
5509 if (RemIdx == 0 && (!IsSubVecPartReg || Vec.isUndef())) in lowerINSERT_SUBVECTOR()