Searched refs:num_compute_rings (Results 1 – 12 of 12) sorted by relevance
194 if (adev->gfx.num_compute_rings > 1 && in amdgpu_gfx_is_high_priority_compute_queue()207 adev->gfx.num_compute_rings); in amdgpu_gfx_compute_queue_acquire()442 j = i + xcc_id * adev->gfx.num_compute_rings; in amdgpu_gfx_mqd_sw_init()483 j = i + xcc_id * adev->gfx.num_compute_rings; in amdgpu_gfx_mqd_sw_fini()523 adev->gfx.num_compute_rings)) { in amdgpu_gfx_disable_kcq()529 j = i + xcc_id * adev->gfx.num_compute_rings; in amdgpu_gfx_disable_kcq()641 j = i + xcc_id * adev->gfx.num_compute_rings; in amdgpu_gfx_mes_enable_kcq()688 adev->gfx.num_compute_rings + in amdgpu_gfx_enable_kcq()1807 if (adev->gfx.num_compute_rings) { in amdgpu_gfx_sysfs_reset_mask_init()1824 if (adev->gfx.num_compute_rings) in amdgpu_gfx_sysfs_reset_mask_fini()[all …]
988 (ring_id + xcc_id * adev->gfx.num_compute_rings) * in gfx_v9_4_3_compute_ring_init()2152 for (j = 0; j < adev->gfx.num_compute_rings; j++) { in gfx_v9_4_3_xcc_kcq_fini_register()2181 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_4_3_xcc_kcq_resume()2183 adev->gfx.num_compute_rings]; in gfx_v9_4_3_xcc_kcq_resume()2218 for (j = 0; j < adev->gfx.num_compute_rings; j++) { in gfx_v9_4_3_xcc_cp_resume()2220 [j + xcc_id * adev->gfx.num_compute_rings]; in gfx_v9_4_3_xcc_cp_resume()3270 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_4_3_eop_irq()3273 xcc_id * adev->gfx.num_compute_rings]; in gfx_v9_4_3_eop_irq()3306 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_4_3_fault()3309 xcc_id * adev->gfx.num_compute_rings]; in gfx_v9_4_3_fault()[all …]
289 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in suspend_resume_compute_scheduler()
774 mec_hpd_size = adev->gfx.num_compute_rings * GFX12_MEC_HPD_SIZE; in gfx_v12_0_mec_init()1346 unsigned num_compute_rings; in gfx_v12_0_sw_init() local1387 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * in gfx_v12_0_sw_init()1389 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, in gfx_v12_0_sw_init()1390 num_compute_rings); in gfx_v12_0_sw_init()1557 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v12_0_sw_fini()3341 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v12_0_kcq_resume()3404 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v12_0_cp_resume()4785 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v12_0_eop_irq()4948 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v12_0_handle_priv_fault()[all …]
1325 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()2063 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()4361 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()4696 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()4723 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()4791 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()4998 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()5093 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()6617 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_eop_irq()6647 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_fault()[all …]
2718 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()3021 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()3031 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()4149 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v7_0_early_init()4455 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()4802 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()4827 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_fault()5089 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
410 unsigned num_compute_rings; member
956 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; in gfx_v11_0_mec_init()1834 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_sw_fini()4453 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_kcq_resume()4519 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_cp_resume()4981 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_check_soft_reset()5065 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v11_0_early_init()6332 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_eop_irq()6495 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_handle_priv_fault()6976 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_set_ring_funcs()
3047 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v6_0_early_init()3099 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v6_0_sw_init()3132 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_sw_fini()3524 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_set_ring_funcs()
1883 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; in gfx_v9_0_mec_init()2443 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_sw_fini()3904 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_resume()3959 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_cp_resume()4782 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v9_0_early_init()6242 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_eop_irq()6272 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_fault()7655 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_set_ring_funcs()
4428 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; in gfx_v10_0_mec_init()4989 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_sw_fini()7173 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_kcq_resume()7227 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_cp_resume()7782 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v10_0_early_init()9190 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_eop_irq()9352 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_handle_priv_fault()9929 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_set_ring_funcs()
397 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_hw_ip_info()