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Searched refs:mmCP_MEM_SLP_CNTL (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c93 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
224 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
H A Dsi.c551 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
648 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
748 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
828 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
905 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
H A Dgfx_v6_0.c2591 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2594 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
2615 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v6_0_enable_mgcg()
2618 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v6_0_enable_mgcg()
H A Dgfx_v8_0.c305 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
468 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
675 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
708 mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
5457 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_get_clockgating_state()
5676 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v8_0_update_medium_grain_clock_gating()
5679 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v8_0_update_medium_grain_clock_gating()
H A Dgfx_v7_0.c3537 orig = data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3540 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
3590 data = RREG32(mmCP_MEM_SLP_CNTL); in gfx_v7_0_enable_mgcg()
3593 WREG32(mmCP_MEM_SLP_CNTL, data); in gfx_v7_0_enable_mgcg()
H A Dgfx_v9_0.c4969 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
4972 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
4998 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v9_0_update_medium_grain_clock_gating()
5001 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v9_0_update_medium_grain_clock_gating()
5305 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v9_0_get_clockgating_state()
H A Dgfx_v10_0.c7929 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7932 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
7948 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL); in gfx_v10_0_update_medium_grain_clock_gating()
7951 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data); in gfx_v10_0_update_medium_grain_clock_gating()
8492 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL)); in gfx_v10_0_get_clockgating_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h455 #define mmCP_MEM_SLP_CNTL 0x3079 macro
H A Dgfx_7_0_d.h255 #define mmCP_MEM_SLP_CNTL 0x3079 macro
H A Dgfx_7_2_d.h257 #define mmCP_MEM_SLP_CNTL 0x3079 macro
H A Dgfx_8_0_d.h289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
H A Dgfx_8_1_d.h289 #define mmCP_MEM_SLP_CNTL 0x3079 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2482 #define mmCP_MEM_SLP_CNTL … macro
H A Dgc_9_1_offset.h2759 #define mmCP_MEM_SLP_CNTL … macro
H A Dgc_9_2_1_offset.h2697 #define mmCP_MEM_SLP_CNTL … macro
H A Dgc_10_1_0_offset.h4821 #define mmCP_MEM_SLP_CNTL … macro
H A Dgc_10_3_0_offset.h4484 #define mmCP_MEM_SLP_CNTL … macro