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Searched refs:csr_set (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/arch/riscv/include/asm/
H A Dirqflags.h21 csr_set(CSR_STATUS, SR_IE); in arch_local_irq_enable()
51 csr_set(CSR_STATUS, flags & SR_IE); in arch_local_irq_restore()
H A Dvector.h110 csr_set(CSR_SSTATUS, SR_VS_THEAD); in riscv_v_enable()
112 csr_set(CSR_SSTATUS, SR_VS); in riscv_v_enable()
H A Dcsr.h553 #define csr_set(csr, val) \ macro
/linux-6.15/drivers/irqchip/
H A Dirq-riscv-intc.c63 csr_set(CSR_IEH, BIT(d->hwirq - BITS_PER_LONG)); in riscv_intc_irq_unmask()
65 csr_set(CSR_IE, BIT(d->hwirq)); in riscv_intc_irq_unmask()
88 csr_set(CSR_IE, mask); in andes_intc_irq_unmask()
90 csr_set(ANDES_CSR_SLIE, mask); in andes_intc_irq_unmask()
H A Dirq-riscv-imsic-state.c50 csr_set(CSR_IREG, val); in imsic_csr_set()
/linux-6.15/arch/riscv/kernel/
H A Dkernel_mode_fpu.c18 csr_set(CSR_SSTATUS, SR_FS); in kernel_fpu_begin()
H A Dprocess.c363 csr_set(CSR_ENVCFG, value); in try_to_set_pmm()
/linux-6.15/tools/testing/selftests/kvm/include/riscv/
H A Darch_timer.h42 csr_set(CSR_SIE, IE_TIE); in timer_irq_enable()
H A Dprocessor.h169 csr_set(CSR_SSTATUS, SR_SIE); in local_irq_enable()
/linux-6.15/arch/riscv/kvm/
H A Daia.c485 csr_set(CSR_HGEIE, BIT(hgei)); in kvm_riscv_aia_wakeon_hgei()
590 csr_set(CSR_HIE, BIT(IRQ_S_GEXT)); in kvm_riscv_aia_enable()
593 csr_set(CSR_HVIEN, BIT(IRQ_PMU_OVF)); in kvm_riscv_aia_enable()
H A Daia_imsic.c181 csr_set(CSR_VSIREG, __v); \
/linux-6.15/drivers/clocksource/
H A Dtimer-clint.c117 csr_set(CSR_IE, IE_TIE); in clint_clock_next_event()
/linux-6.15/tools/arch/riscv/include/asm/
H A Dcsr.h514 #define csr_set(csr, val) \ macro
/linux-6.15/tools/testing/selftests/kvm/riscv/
H A Dsbi_pmu_test.c489 csr_set(CSR_IE, BIT(IRQ_PMU_OVF)); in test_pmu_events_overflow()