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Searched refs:amdgpu_ring_emit_wreg (Results 1 – 25 of 27) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c51 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v4_0_flush_hdp()
67 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v4_0_invalidate_hdp()
H A Dhdp_v5_0.c42 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v5_0_flush_hdp()
53 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET( in hdp_v5_0_invalidate_hdp()
H A Dgmc_v12_0.c384 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v12_0_emit_flush_gpu_tlb()
388 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v12_0_emit_flush_gpu_tlb()
404 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v12_0_emit_flush_gpu_tlb()
425 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v12_0_emit_pasid_mapping()
H A Dgmc_v11_0.c364 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v11_0_emit_flush_gpu_tlb()
368 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v11_0_emit_flush_gpu_tlb()
384 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v11_0_emit_flush_gpu_tlb()
405 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v11_0_emit_pasid_mapping()
H A Dgmc_v10_0.c399 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v10_0_emit_flush_gpu_tlb()
403 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v10_0_emit_flush_gpu_tlb()
419 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v10_0_emit_flush_gpu_tlb()
440 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v10_0_emit_pasid_mapping()
H A Dhdp_v7_0.c42 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v7_0_flush_hdp()
H A Dhdp_v6_0.c45 …amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> … in hdp_v6_0_flush_hdp()
H A Dhdp_v5_2.c48 amdgpu_ring_emit_wreg(ring, in hdp_v5_2_flush_hdp()
H A Dgmc_v7_0.c486 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v7_0_emit_flush_gpu_tlb()
489 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v7_0_emit_flush_gpu_tlb()
497 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v7_0_emit_pasid_mapping()
H A Dgmc_v6_0.c370 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v6_0_emit_flush_gpu_tlb()
373 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v6_0_emit_flush_gpu_tlb()
H A Dgmc_v9_0.c1010 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in gmc_v9_0_emit_flush_gpu_tlb()
1014 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in gmc_v9_0_emit_flush_gpu_tlb()
1030 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem + in gmc_v9_0_emit_flush_gpu_tlb()
1051 amdgpu_ring_emit_wreg(ring, reg, pasid); in gmc_v9_0_emit_pasid_mapping()
H A Dgmc_v8_0.c677 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12); in gmc_v8_0_emit_flush_gpu_tlb()
680 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid); in gmc_v8_0_emit_flush_gpu_tlb()
688 amdgpu_ring_emit_wreg(ring, mmIH_VMID_0_LUT + vmid, pasid); in gmc_v8_0_emit_pasid_mapping()
H A Dsdma_v6_0.c1228 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in sdma_v6_0_ring_emit_vm_flush()
1231 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in sdma_v6_0_ring_emit_vm_flush()
1275 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v6_0_ring_emit_reg_write_reg_wait()
H A Dsdma_v5_2.c1217 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + in sdma_v5_2_ring_emit_vm_flush()
1220 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + in sdma_v5_2_ring_emit_vm_flush()
1264 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_2_ring_emit_reg_write_reg_wait()
H A Damdgpu_ring.h333 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) macro
H A Dcik.c1864 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in cik_flush_hdp()
1875 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in cik_invalidate_hdp()
H A Damdgpu_ring.c448 amdgpu_ring_emit_wreg(ring, reg0, ref); in amdgpu_ring_emit_reg_write_reg_wait_helper()
H A Dvi.c1317 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in vi_flush_hdp()
1328 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in vi_invalidate_hdp()
H A Dsi.c1489 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); in si_flush_hdp()
1500 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); in si_invalidate_hdp()
H A Dsdma_v7_0.c1304 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v7_0_ring_emit_reg_write_reg_wait()
H A Dsdma_v5_0.c1386 amdgpu_ring_emit_wreg(ring, reg0, ref); in sdma_v5_0_ring_emit_reg_write_reg_wait()
H A Damdgpu_gfx.c1148 amdgpu_ring_emit_wreg(ring, reg, v); in amdgpu_kiq_wreg()
H A Dgfx_v9_4_3.c3392 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_4_3_emit_wave_limit_cs()
3406 amdgpu_ring_emit_wreg(ring, in gfx_v9_4_3_emit_wave_limit()
H A Dgfx_v9_0.c5755 amdgpu_ring_emit_wreg(ring, in gfx_v9_0_ring_preempt_ib()
7149 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v9_0_emit_wave_limit_cs()
7164 amdgpu_ring_emit_wreg(ring, in gfx_v9_0_emit_wave_limit()
H A Dgfx_v8_0.c6841 amdgpu_ring_emit_wreg(ring, wcl_cs_reg, val); in gfx_v8_0_emit_wave_limit_cs()
6857 amdgpu_ring_emit_wreg(ring, mmSPI_WCL_PIPE_PERCENT_GFX, val); in gfx_v8_0_emit_wave_limit()

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