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Searched refs:getInstr (Results 1 – 25 of 90) sorted by relevance

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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp31 if (QII->mayBeCurLoad(*SUd->getInstr())) in hasDependence()
34 if (QII->canExecuteInBundle(*SUd->getInstr(), *SUu->getInstr())) in hasDependence()
57 if (SU->isInstr() && QII.mayBeCurLoad(*SU->getInstr())) { in SchedulingCost()
H A DHexagonSubtarget.cpp268 MachineInstr &MI1 = *SU.getInstr(); in apply()
329 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
393 MachineInstr &L0 = *S0.getInstr(); in apply()
406 MachineInstr &L1 = *S1.getInstr(); in apply()
445 MachineInstr *SrcInst = Src->getInstr(); in adjustSchedDependency()
446 MachineInstr *DstInst = Dst->getInstr(); in adjustSchedDependency()
558 MachineInstr *SrcI = Src->getInstr(); in restoreLatency()
579 MachineInstr *DstI = Dst->getInstr(); in restoreLatency()
626 !I.getSUnit()->getInstr()->isPseudo()) in getZeroLatency()
638 MachineInstr &SrcInst = *Src->getInstr(); in isBestZeroLatency()
[all …]
H A DHexagonHazardRecognizer.cpp40 MachineInstr *MI = SU->getInstr(); in getHazardType()
98 if (UsesLoad && SU->isInstr() && SU->getInstr()->mayLoad()) in ShouldPreferAnother()
113 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
165 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
166 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
H A DHexagonVLIWPacketizer.cpp422 if (PacketSU->getInstr()->isInlineAsm()) in canPromoteToDotCur()
516 assert(SUI->getInstr() && SUJ->getInstr()); in updateOffset()
517 MachineInstr &MI = *SUI->getInstr(); in updateOffset()
518 MachineInstr &MJ = *SUJ->getInstr(); in updateOffset()
673 if (PacketSU->getInstr()->mayStore()) in canPromoteToNewValueStore()
1325 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPacketizeTogether()
1326 MachineInstr &I = *SUI->getInstr(); in isLegalToPacketizeTogether()
1327 MachineInstr &J = *SUJ->getInstr(); in isLegalToPacketizeTogether()
1643 assert(SUI->getInstr() && SUJ->getInstr()); in isLegalToPruneDependencies()
1644 MachineInstr &I = *SUI->getInstr(); in isLegalToPruneDependencies()
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H A DHexagonISelLoweringHVX.cpp1354 return getInstr(Hexagon::A4_vcmpbgtui, dl, ResTy, in extractHvxSubvectorPred()
1550 SDValue Rot = getInstr(Hexagon::V6_valignbi, dl, ByteTy, in compressHvxPred()
2199 SDValue Store = getInstr(StoreOpc, dl, MVT::Other, in LowerHvxMaskedOp()
2226 getInstr(StoreOpc, dl, MVT::Other, in LowerHvxMaskedOp()
2229 getInstr(StoreOpc, dl, MVT::Other, in LowerHvxMaskedOp()
2266 getInstr(Hexagon::V6_vshuffvdd, dl, VecTy, in LowerHvxFpExtend()
2521 SDValue T3 = getInstr(Hexagon::V6_vasrw_acc, dl, VecTy, in emitHvxMulHsV60()
2559 SDValue T0 = getInstr(Hexagon::V6_lvsplatw, dl, VecTy, in emitHvxMulLoHiV60()
2569 SDValue P2 = getInstr(Hexagon::V6_vadduhw, dl, PairTy, in emitHvxMulLoHiV60()
2577 SDValue T4 = getInstr(Hexagon::V6_vasrw_acc, dl, VecTy, in emitHvxMulLoHiV60()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.cpp300 Entries.front().getInstr()->getDebugVariable(); in beginFunction()
303 if (!IsDescribedByReg(Entries.front().getInstr())) in beginFunction()
304 LabelsBeforeInsn[Entries.front().getInstr()] = Asm->getFunctionBegin(); in beginFunction()
305 if (Entries.front().getInstr()->getDebugExpression()->isFragment()) { in beginFunction()
310 const DIExpression *Fragment = I->getInstr()->getDebugExpression(); in beginFunction()
315 Pred.getInstr()->getDebugExpression()); in beginFunction()
322 if (IsDescribedByReg(I->getInstr())) in beginFunction()
324 LabelsBeforeInsn[I->getInstr()] = Asm->getFunctionBegin(); in beginFunction()
331 requestLabelBeforeInsn(Entry.getInstr()); in beginFunction()
333 requestLabelAfterInsn(Entry.getInstr()); in beginFunction()
H A DDbgEntityHistoryCalculator.cpp79 Entries.back().getInstr()->isEquivalentDbgInstr(MI)) { in startDbgValue()
81 << "\t" << Entries.back().getInstr() << "\t" << MI in startDbgValue()
95 if (Entries.back().isClobber() && Entries.back().getInstr() == &MI) in startClobber()
200 const MachineInstr *StartMI = EI->getInstr(); in trimLocationRanges()
271 const MachineInstr *MI = Entry.getInstr(); in hasNonEmptyLocation()
345 if (Entry.getInstr()->isDebugEntryValue()) in clobberRegEntries()
347 if (Entry.getInstr()->hasDebugOperandForReg(RegNo)) { in clobberRegEntries()
350 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
354 for (const auto &MO : Entry.getInstr()->debug_operands()) in clobberRegEntries()
385 const MachineInstr &DV = *Entry.getInstr(); in handleNewDebugValue()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp154 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(), in schedNode()
155 E = SU->getInstr()->operands_end(); It != E; ++It) { in schedNode()
188 if (isPhysicalRegCopy(SU->getInstr())) { in releaseBottomNode()
213 MachineInstr *MI = SU->getInstr(); in getAluKind()
287 int Opcode = SU->getInstr()->getOpcode(); in getInstKind()
316 InstructionsGroupCandidate.push_back(SU->getInstr()); in PopInst()
318 (!AnyALU || !TII->isVectorOnly(*SU->getInstr()))) { in PopInst()
387 AssignSlot(UnslotedSU->getInstr(), Slot); in AttemptFillSlot()
436 InstructionsGroupCandidate.push_back(SU->getInstr()); in pickAlu()
H A DAMDGPUIGroupLP.cpp209 << *SU.getInstr()); in add()
947 auto MI = SU->getInstr(); in apply()
956 if (TII->isDS(*SuccUnit->getInstr()) && in apply()
957 SuccUnit->getInstr()->mayStore()) { in apply()
1017 auto MI = SU->getInstr(); in apply()
1130 auto I = SU.getInstr(); in applyIGLPStrategy()
1173 auto MI = Succ.getSUnit()->getInstr(); in applyIGLPStrategy()
1546 MachineInstr &MI = *SU.getInstr(); in canAddSU()
1614 unsigned Opc = R->getInstr()->getOpcode(); in apply()
1639 MachineInstr &MI = *SchedBarrier.getInstr(); in addSchedBarrierEdges()
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H A DGCNDPPCombine.cpp246 if (TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, SDst)) { in createDPPInst()
292 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) { in createDPPInst()
325 if (!TII->isOperandLegal(*DPPInst.getInstr(), OpNum, Src1)) { in createDPPInst()
345 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
346 !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) { in createDPPInst()
422 DPPInst.getInstr()->eraseFromParent(); in createDPPInst()
425 LLVM_DEBUG(dbgs() << " combined: " << *DPPInst.getInstr()); in createDPPInst()
426 return DPPInst.getInstr(); in createDPPInst()
616 DPPMIs.push_back(UndefInst.getInstr()); in combineDPPMov()
H A DSIMachineScheduler.cpp319 RPTracker.setPos(SU->getInstr()); in initRegPressure()
400 TopRPTracker.setPos(SU->getInstr()); in schedule()
1125 if (SIInstrInfo::isEXP(*SU.getInstr())) { in colorExports()
1137 if (!SIInstrInfo::isEXP(*SuccSU->getInstr())) { in colorExports()
1322 MachineInstr *MI = SU->getInstr(); in scheduleInsideBlocks()
1351 Block->schedule((*SUs.begin())->getInstr(), (*SUs.rbegin())->getInstr()); in scheduleInsideBlocks()
1793 if (SITII->isLowLatencyInstruction(*Pred->getInstr())) { in moveLowLatencies()
1803 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in moveLowLatencies()
1824 } else if (SU->getInstr()->getOpcode() == AMDGPU::COPY) { in moveLowLatencies()
1918 if (SITII->isLowLatencyInstruction(*SU->getInstr())) { in schedule()
[all …]
H A DAMDGPUExportClustering.cpp30 return SIInstrInfo::isEXP(*SU.getInstr()); in isExport()
34 const MachineInstr *MI = SU->getInstr(); in isPositionExport()
H A DGCNVOPDUtils.cpp167 const MachineInstr *IMI = ISUI->getInstr(); in apply()
176 const MachineInstr *JMI = JSUI->getInstr(); in apply()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DMacroFusion.cpp93 dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " in fuseInstructionPair()
94 << DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';); in fuseInstructionPair()
175 if (DAG->ExitSU.getInstr()) in apply()
183 const MachineInstr &AnchorMI = *AnchorSU.getInstr(); in scheduleAdjacentImpl()
202 const MachineInstr *DepMI = DepSU.getInstr(); in scheduleAdjacentImpl()
H A DMachinePipeliner.cpp885 MachineInstr *MI = I.getInstr(); in updatePhiDependences()
941 if (I.getInstr()->isPHI()) { in updatePhiDependences()
1740 if (!SU.getInstr()->isCopy() && !SU.getInstr()->isRegSequence()) in apply()
2423 SU->getInstr()->dump(); in schedulePipeline()
2779 SU->getInstr()->dump(); in insert()
2794 SU->getInstr()->dump(); in insert()
3064 if (UseSU->getInstr()->isPHI()) in isLoopCarried()
3116 if (SU->getInstr()->isPHI()) in computeUnpipelineableNodes()
3340 if (SU->getInstr()->isPHI()) in reorderInstructions()
3345 if (!SU->getInstr()->isPHI()) in reorderInstructions()
[all …]
H A DVLIWMachineScheduler.cpp109 if (!SU || !SU->getInstr()) in isResourceAvailable()
114 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
116 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
162 switch (SU->getInstr()->getOpcode()) { in reserveResources()
164 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
186 LLVM_DEBUG(Packet[i]->getInstr()->dump()); in reserveResources()
326 assert(SU->getInstr() && "Scheduled SUnit must have instr"); in releaseBottomNode()
365 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard()
432 IssueCount += SchedModel->getNumMicroOps(SU->getInstr()); in bumpNode()
532 TempTracker.getMaxPressureDelta((*I)->getInstr(), RPDelta, in readyQueueVerboseDump()
[all …]
H A DScheduleDAGInstrs.cpp271 UseInstr = UseSU->getInstr(); in addPhysRegDataDeps()
295 MachineInstr *MI = SU->getInstr(); in addPhysRegDeps()
317 MachineInstr *DefInstr = DefSU->getInstr(); in addPhysRegDeps()
404 MachineInstr *MI = SU->getInstr(); in addVRegDefDeps()
452 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps()
523 const MachineInstr *MI = SU->getInstr(); in addVRegUseDeps()
557 if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) { in addChainDependency()
1181 SU.getInstr()->dump(); in dumpNode()
1187 if (EntrySU.getInstr() != nullptr) in dump()
1191 if (ExitSU.getInstr() != nullptr) in dump()
[all …]
H A DSlotIndexes.cpp125 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeMachineInstrFromMaps()
138 assert(MIEntry.getInstr() == &MI && "Instruction indexes broken."); in removeSingleMachineInstrFromMaps()
208 MachineInstr *SlotMI = ListI->getInstr(); in repairIndexesInRange()
250 if (ILE.getInstr()) { in dump()
251 dbgs() << *ILE.getInstr(); in dump()
H A DMachineScheduler.cpp832 MachineInstr *MI = SU->getInstr(); in schedule()
1156 const MachineInstr &MI = *SU.getInstr(); in collectVRegUses()
1392 if (EntrySU.getInstr() != nullptr) in dump()
1408 if (ExitSU.getInstr() != nullptr) in dump()
1615 MachineInstr *MI = SU->getInstr(); in scheduleMI()
2176 if (!SU.getInstr()->isCopy()) in apply()
3453 Cand.SU->getInstr(), in initCandidate()
3460 Cand.SU->getInstr(), in initCandidate()
3467 Cand.SU->getInstr(), in initCandidate()
3747 << *SU->getInstr()); in pickNode()
[all …]
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp105 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in fitsIntoCurrentGroup()
169 OS << TII->getName(SU->getInstr()->getOpcode()); in dumpSU()
204 if (has4RegOps(SU->getInstr())) in dumpSU()
285 LastEmittedMI = SU->getInstr(); in EmitInstruction()
291 LastEmittedMI = SU->getInstr(); in EmitInstruction()
329 CurrGroupHas4RegOps |= has4RegOps(SU->getInstr()); in EmitInstruction()
364 if (CurrGroupSize == 2 && has4RegOps(SU->getInstr())) in groupingCost()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
26 Cand.SU->getInstr()->getOpcode() == PPC::ADDI8; in isADDIInstr()
37 if (isADDIInstr(FirstCand) && SecondCand.SU->getInstr()->mayLoad()) { in biasAddiLoadCandidate()
41 if (FirstCand.SU->getInstr()->mayLoad() && isADDIInstr(SecondCand)) { in biasAddiLoadCandidate()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp47 MachineInstr *MI = SU->getInstr(); in getHazardType()
90 MachineInstr *MI = SU->getInstr(); in EmitInstruction()
185 MachineInstr &L0 = *SU->getInstr(); in getHazardType()
257 MachineInstr &MI = *SU->getInstr(); in EmitInstruction()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp375 LLVM_DEBUG(dbgs() << "Remove " << *MIB.getInstr() << '\n'); in ExpandMOVX_RR()
378 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to MOV\n"); in ExpandMOVX_RR()
390 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); in ExpandMOVSZX_RR()
422 BuildMI(MBB, MIB.getInstr(), DL, get(Move), Dst).addReg(SSrc); in ExpandMOVSZX_RR()
427 AddSExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
430 AddZExt(MBB, MIB.getInstr(), DL, Dst, MVTSrc, MVTDst); in ExpandMOVSZX_RR()
441 LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to LOAD and "); in ExpandMOVSZX_RM()
459 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandMOVSZX_RM()
477 MachineBasicBlock::iterator I = MIB.getInstr(); in ExpandPUSH_POP()
513 auto MI = MIB.getInstr(); in ExpandMOVEM()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MachineScheduler.cpp66 MachineInstr *Instr0 = TryCand.SU->getInstr(); in tryCandidate()
67 MachineInstr *Instr1 = Cand.SU->getInstr(); in tryCandidate()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSlotIndexes.h52 MachineInstr* getInstr() const { return mi; } in getInstr() function
390 return index.listEntry()->getInstr();
399 if (I->getInstr())
586 assert(miEntry->getInstr() == &MI &&

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