209                       << *SU.getInstr());  in add()
250   assert(SU.getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER ||  in resetEdges()
251          SU.getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER ||  in resetEdges()
252          SU.getInstr()->getOpcode() == AMDGPU::IGLP_OPT);  in resetEdges()
403         return SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER;  in reset()
461         if (SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)  in makePipeline()
919           if (TII->isMFMAorWMMA(*Elt.getInstr())) {  in apply()
947       auto MI = SU->getInstr();  in apply()
956           if (TII->isDS(*SuccUnit->getInstr()) &&  in apply()
957               SuccUnit->getInstr()->mayStore()) {  in apply()
1017       auto MI = SU->getInstr();  in apply()
1028         auto Op = Elt->getInstr()->getOperand(0);  in apply()
1077             if (Pred.getSUnit()->getInstr()->getOpcode() ==  in apply()
1130     auto I = SU.getInstr();  in applyIGLPStrategy()
1139           if (Pred.getSUnit()->getInstr()->getOpcode() ==  in applyIGLPStrategy()
1166         if (Pred.getSUnit()->getInstr()->getOpcode() != AMDGPU::V_PERM_B32_e64)  in applyIGLPStrategy()
1173           auto MI = Succ.getSUnit()->getInstr();  in applyIGLPStrategy()
1497     if (A == B || A->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)  in link()
1520     if (A->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)  in link()
1546   MachineInstr &MI = *SU.getInstr();  in canAddSU()
1614     unsigned Opc = R->getInstr()->getOpcode();  in apply()
1639   MachineInstr &MI = *SchedBarrier.getInstr();  in addSchedBarrierEdges()
1702   MachineInstr &SGB = *RIter->getInstr();  in initSchedGroupBarrierPipelineStage()
1716       (IGLPStrategyID)SU.getInstr()->getOperand(0).getImm();  in initIGLPOpt()