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Searched refs:PartVT (Results 1 – 14 of 14) sorted by relevance

/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp233 } else if (PartVT.isFloatingPoint()) { in getCopyFromParts()
527 EVT PartEVT = PartVT; in getCopyToParts()
534 unsigned PartBits = PartVT.getSizeInBits(); in getCopyToParts()
547 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && in getCopyToParts()
552 if (PartVT == MVT::x86mmx) in getCopyToParts()
561 assert((PartVT.isInteger() || PartVT == MVT::x86mmx) && in getCopyToParts()
566 if (PartVT == MVT::x86mmx) in getCopyToParts()
641 if (!PartVT.isVector()) in widenVectorToPartType()
670 return DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in widenVectorToPartType()
696 EVT PartEVT = PartVT; in getCopyToPartsVector()
[all …]
H A DLegalizeVectorTypes.cpp5290 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_EXTRACT_SUBVECTOR() local
5293 if (getTypeAction(PartVT) != TargetLowering::TypeWidenVector) { in WidenVecRes_EXTRACT_SUBVECTOR()
5298 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, PartVT, InOp, in WidenVecRes_EXTRACT_SUBVECTOR()
5301 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_EXTRACT_SUBVECTOR()
5894 EVT PartVT = EVT::getVectorVT(*DAG.getContext(), EltVT, in WidenVecRes_VECTOR_REVERSE() local
5902 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, PartVT, ReverseVal, in WidenVecRes_VECTOR_REVERSE()
5905 Parts.push_back(DAG.getUNDEF(PartVT)); in WidenVecRes_VECTOR_REVERSE()
/freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1629 EVT PartVT = VT; in getVectorTypeBreakdown() local
1632 LK = getTypeConversion(Context, PartVT); in getVectorTypeBreakdown()
1633 PartVT = LK.second; in getVectorTypeBreakdown()
1636 if (!PartVT.isVector()) { in getVectorTypeBreakdown()
1643 PartVT.getVectorElementCount().getKnownMinValue()); in getVectorTypeBreakdown()
1644 IntermediateVT = PartVT; in getVectorTypeBreakdown()
1748 MVT PartVT = in GetReturnInfo() local
1763 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); in GetReturnInfo()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h585 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
589 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DSystemZISelLowering.cpp1554 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
1556 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in splitValueIntoRegisterParts()
1567 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1568 if (ValueVT.getSizeInBits() == 128 && NumParts == 1 && PartVT == MVT::Untyped) { in joinRegisterPartsIntoValue()
1922 MVT PartVT = getRegisterTypeForCallingConv(Ctx, CLI.CallConv, OrigArgVT); in LowerCall() local
1924 SlotVT = EVT::getIntegerVT(Ctx, PartVT.getSizeInBits() * N); in LowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h728 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
733 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DRISCVISelLowering.cpp2183 if (RV64LegalI32 && Subtarget.is64Bit() && PartVT == MVT::i32) in getRegisterTypeForCallingConv()
2186 return PartVT; in getRegisterTypeForCallingConv()
18448 EVT PartVT = PartValue.getValueType(); in LowerCall() local
18449 if (PartVT.isScalableVector()) in LowerCall()
18451 StoredSize += PartVT.getStoreSize(); in LowerCall()
19848 PartVT == MVT::f32) { in splitValueIntoRegisterParts()
19863 EVT PartEltVT = PartVT.getVectorElementType(); in splitValueIntoRegisterParts()
19884 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
19887 DAG.getNode(ISD::INSERT_SUBVECTOR, DL, PartVT, DAG.getUNDEF(PartVT), in splitValueIntoRegisterParts()
19902 PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
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/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h908 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
913 unsigned NumParts, MVT PartVT, EVT ValueVT,
H A DARMISelLowering.cpp4443 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4445 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
4447 unsigned PartBits = PartVT.getSizeInBits(); in splitValueIntoRegisterParts()
4450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); in splitValueIntoRegisterParts()
4459 MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4460 if ((ValueVT == MVT::f16 || ValueVT == MVT::bf16) && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
4462 unsigned PartBits = PartVT.getSizeInBits(); in joinRegisterPartsIntoValue()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1158 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
H A DPPCISelLowering.cpp18260 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
18266 if (PartVT == MVT::f64 && in splitValueIntoRegisterParts()
/freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h4320 unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const { in splitValueIntoRegisterParts() argument
4345 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp4163 EVT PartVT = PartValue.getValueType(); in LowerCall() local
4165 StoredSize += PartVT.getStoreSize(); in LowerCall()
4166 StackAlign = std::max(StackAlign, getPrefTypeAlign(PartVT, DAG)); in LowerCall()
/freebsd-14.2/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp798 MVT PartVT = MVT::getVectorVT(VecTy.getVectorElementType(), OpsPerWord); in buildHvxVectorReg() local
800 SDValue W = buildVector32(Values.slice(i, OpsPerWord), dl, PartVT, DAG); in buildHvxVectorReg()