| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/PBQP/ |
| H A D | Math.h | 121 class Matrix { 140 Matrix(const Matrix &M) in Matrix() function 147 Matrix(Matrix &&M) in Matrix() function 205 Matrix transpose() const { in transpose() 207 Matrix M(Cols, Rows); in transpose() 215 Matrix& operator+=(const Matrix &M) { 224 Matrix operator+(const Matrix &M) { 226 Matrix Tmp(*this); 272 class MDMatrix : public Matrix { 274 MDMatrix(const Matrix &m) : Matrix(m), md(*this) {} in MDMatrix() [all …]
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| H A D | ReductionRules.h | 34 using Matrix = typename GraphT::Matrix; in applyR1() local 43 const Matrix &ECosts = G.getEdgeCosts(EId); in applyR1() 78 using Matrix = typename GraphT::Matrix; in applyR2() local 96 const Matrix *YXECosts = FlipEdge1 ? in applyR2() 97 new Matrix(G.getEdgeCosts(YXEId).transpose()) : in applyR2() 100 const Matrix *ZXECosts = FlipEdge2 ? in applyR2() 101 new Matrix(G.getEdgeCosts(ZXEId).transpose()) : in applyR2() 134 const Matrix &YZECosts = G.getEdgeCosts(YZEId); in applyR2() 182 using Matrix = typename GraphT::Matrix; in backpropagate() local 203 const Matrix& edgeCosts = G.getEdgeCosts(EId); in backpropagate()
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| H A D | Graph.h | 54 using Matrix = typename SolverT::Matrix; variable 530 const Matrix& getEdgeCosts(EdgeId EId) const { in getEdgeCosts()
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| H A D | CostAllocator.h | 114 using Matrix = MatrixT; variable
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InterleavedAccess.cpp | 319 ArrayRef<Instruction *> Matrix, in interleave8bitStride4VF8() argument 345 Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow); in interleave8bitStride4VF8() 347 Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow); in interleave8bitStride4VF8() 397 IntrVec[0] = Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskLow); in interleave8bitStride4() 398 IntrVec[1] = Builder.CreateShuffleVector(Matrix[0], Matrix[1], MaskHigh); in interleave8bitStride4() 399 IntrVec[2] = Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskLow); in interleave8bitStride4() 400 IntrVec[3] = Builder.CreateShuffleVector(Matrix[2], Matrix[3], MaskHigh); in interleave8bitStride4() 693 Value *IntrVec1 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask); in transpose_4x4() 694 Value *IntrVec2 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask); in transpose_4x4() 699 Value *IntrVec3 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask); in transpose_4x4() [all …]
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| H A D | X86RegisterInfo.h | 178 const LiveRegMatrix *Matrix) const override;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRegMatrix.cpp | 61 if (NumRegUnits != Matrix.size()) in runOnMachineFunction() 63 Matrix.init(LIUAlloc, NumRegUnits); in runOnMachineFunction() 71 for (unsigned i = 0, e = Matrix.size(); i != e; ++i) { in releaseMemory() 72 Matrix[i].clear(); in releaseMemory() 113 Matrix[Unit].unify(VirtReg, Range); in assign() 130 Matrix[Unit].extract(VirtReg, Range); in unassign() 140 if (!Matrix[Unit].empty()) in isPhysRegUsed() 181 Q.init(UserTag, LR, Matrix[RegUnit]); in query() 233 Q.reset(UserTag, LR, Matrix[Unit]); in checkInterference() 243 if ((VRegInterval = Matrix[Unit].getOneVReg())) in getOneVReg()
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| H A D | RegAllocBasic.cpp | 149 Matrix->unassign(LI); in INITIALIZE_PASS_DEPENDENCY() 167 Matrix->unassign(LI); in LRE_WillShrinkVirtReg() 217 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in spillInterferences() 238 Matrix->unassign(Spill); in spillInterferences() 266 AllocationOrder::create(VirtReg.reg(), *VRM, RegClassInfo, Matrix); in selectOrSplit() 270 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit() 291 assert(!Matrix->checkInterference(VirtReg, PhysReg) && in selectOrSplit()
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| H A D | AllocationOrder.cpp | 31 const LiveRegMatrix *Matrix) { in create() argument 37 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix); in create()
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| H A D | RegAllocBase.cpp | 63 Matrix = &mat; in init() 100 Matrix->invalidateVirtRegs(); in allocatePhysRegs() 144 Matrix->assign(*VirtReg, AvailablePhysReg); in allocatePhysRegs()
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| H A D | RegAllocGreedy.cpp | 239 Matrix->unassign(LI); in LRE_CanEraseVirtReg() 257 Matrix->unassign(LI); in LRE_WillShrinkVirtReg() 512 Matrix->unassign(*Intf); in evictInterference() 2029 Matrix->unassign(*RC); in tryLastChanceRecoloring() 2035 Matrix->assign(VirtReg, PhysReg); in tryLastChanceRecoloring() 2048 Matrix->unassign(VirtReg); in tryLastChanceRecoloring() 2057 Matrix->unassign(VirtReg); in tryLastChanceRecoloring() 2081 Matrix->unassign(*LI); in tryLastChanceRecoloring() 2134 Matrix->assign(*LI, PhysReg); in tryRecoloringCandidates() 2350 Matrix->unassign(LI); in tryHintRecoloring() [all …]
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| H A D | RegAllocEvictionAdvisor.cpp | 127 : MF(MF), RA(RA), Matrix(RA.getInterferenceMatrix()), in RegAllocEvictionAdvisor() 189 if (Matrix->checkInterference(VirtReg, PhysReg) > LiveRegMatrix::IK_VirtReg) in canEvictInterferenceBasedOnCost() 205 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, Unit); in canEvictInterferenceBasedOnCost()
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| H A D | RegAllocBase.h | 69 LiveRegMatrix *Matrix = nullptr; variable
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| H A D | AllocationOrder.h | 86 const LiveRegMatrix *Matrix);
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| H A D | RegAllocEvictionAdvisor.h | 139 LiveRegMatrix *const Matrix; variable
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | MatrixBuilder.h | 89 CallInst *CreateColumnMajorStore(Value *Matrix, Value *Ptr, Align Alignment, 93 Value *Ops[] = {Matrix, Ptr, 96 Type *OverloadedTypes[] = {Matrix->getType(), Stride->getType()}; 110 CallInst *CreateMatrixTranspose(Value *Matrix, unsigned Rows, 112 auto *OpType = cast<VectorType>(Matrix->getType()); 117 Value *Ops[] = {Matrix, B.getInt32(Rows), B.getInt32(Columns)}; 146 Value *CreateMatrixInsert(Value *Matrix, Value *NewVal, Value *RowIdx, in CreateMatrixInsert() argument 149 Matrix, NewVal, in CreateMatrixInsert()
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | atmel-matrix.txt | 1 * Device tree bindings for Atmel Bus Matrix 3 The Bus Matrix registers are used to configure Atmel SoCs internal bus 17 - reg: Contains offset/length value of the Bus Matrix
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 43 LiveRegMatrix *Matrix; member in __anon2734261d0111::SIPreAllocateWWMRegs 107 Matrix->checkInterference(LI, PhysReg) == LiveRegMatrix::IK_Free) { in processDef() 108 Matrix->assign(LI, PhysReg); in processDef() 201 Matrix = &getAnalysis<LiveRegMatrix>(); in runOnMachineFunction()
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| /freebsd-14.2/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | LiveRegMatrix.h | 50 LiveIntervalUnion::Array Matrix; variable 157 LiveIntervalUnion *getLiveUnions() { return &Matrix[0]; } in getLiveUnions()
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| H A D | RegAllocPBQP.h | 55 MatrixMetadata(const Matrix& M) in MatrixMetadata() 276 using RawMatrix = PBQP::Matrix; 278 using Matrix = RAMatrix; variable 279 using CostAllocator = PBQP::PoolCostAllocator<Vector, Matrix>; 328 void handleUpdateCosts(EdgeId EId, const Matrix& NewCosts) { in handleUpdateCosts()
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| /freebsd-14.2/sys/contrib/device-tree/src/arm/ |
| H A D | armada-xp-matrix.dts | 3 * Device Tree file for Marvell Armada XP Matrix board 14 model = "Marvell Armada XP Matrix Board";
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRegisterInfo.h | 101 const LiveRegMatrix *Matrix) const override;
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| /freebsd-14.2/sys/contrib/device-tree/Bindings/input/ |
| H A D | matrix-keymap.yaml | 7 title: Common Key Matrices on Matrix-connected Key Boards
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.h | 152 const LiveRegMatrix *Matrix) const override;
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| /freebsd-14.2/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | P10InstrResources.td | 1460 // 10 Cycles SIMD Matrix Multiply Engine operations, 0 input operands 1466 // 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1479 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1505 // 10 Cycles SIMD Matrix Multiply Engine operations, 2 input operands 1518 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 input operands 1545 // 10 Cycles SIMD Matrix Multiply Engine operations, and 3 Cycles ALU operations, 1 input operands 1552 // 10 Cycles SIMD Matrix Multiply Engine operations, 3 Cycles ALU operations, 10 Cycles SIMD Matrix…
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