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Searched refs:isBeforeLegalizeOps (Results 1 – 12 of 12) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp596 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
2304 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
3200 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
3526 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3535 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3764 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3817 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3935 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3955 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4198 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp568 if (DCI.isBeforeLegalizeOps()) in performDivRemCombine()
677 if (DCI.isBeforeLegalizeOps()) in performSELECTCombine()
758 if (DCI.isBeforeLegalizeOps()) in performCMovFPCombine()
785 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
871 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
1059 if (DCI.isBeforeLegalizeOps()) { in performSUBCombine()
1074 if (DCI.isBeforeLegalizeOps()) { in performADDCombine()
1109 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) in performSHLCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1607 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1623 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp12404 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
12617 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
12862 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFpToIntCombine()
12935 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFDivCombine()
13153 if (DCI.isBeforeLegalizeOps()) in performSVEAndCombine()
13495 if (DCI.isBeforeLegalizeOps()) in performConcatVectorsCombine()
13587 if (DCI.isBeforeLegalizeOps()) in tryCombineFixedPointConvert()
13899 if (DCI.isBeforeLegalizeOps()) in performAddSubLongCombine()
13960 if (DCI.isBeforeLegalizeOps()) in tryCombineLongOpWithDup()
15112 if (DCI.isBeforeLegalizeOps()) in performPostLD1Combine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp39972 if (!DCI.isBeforeLegalizeOps()) in combineCastedMaskArithmetic()
40805 if (DCI.isBeforeLegalizeOps()) in combineExtractWithShuffle()
44888 if (DCI.isBeforeLegalizeOps()) in combineAnd()
45254 if (DCI.isBeforeLegalizeOps()) in combineOr()
47505 if (DCI.isBeforeLegalizeOps()) in combineXor()
48160 if (!DCI.isBeforeLegalizeOps()) in combineToExtendBoolVectorInReg()
48324 if (!DCI.isBeforeLegalizeOps()) in combineSext()
48478 if (DCI.isBeforeLegalizeOps()) in combineZext()
48969 if (DCI.isBeforeLegalizeOps()) { in combineGatherScatter()
50393 if (DCI.isBeforeLegalizeOps()) in combineInsertSubvector()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3537 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } in isBeforeLegalizeOps() function
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1903 if (DCI.isBeforeLegalizeOps() || in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp4187 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
H A DSIISelLowering.cpp9328 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps()) in performOrCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2239 if (DCI.isBeforeLegalizeOps()) in PerformHvxDAGCombine()
H A DHexagonISelLowering.cpp3276 if (DCI.isBeforeLegalizeOps()) in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16947 bool LegalOps = !DCI.isBeforeLegalizeOps(); in combineFMALike()