Lines Matching refs:isBeforeLegalizeOps
596 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
2304 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
3200 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
3526 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3535 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3764 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3817 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3935 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3955 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3971 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
3989 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4074 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
4198 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
4244 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
5500 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareUREMEqFold()
5637 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::SUB, VT)) in prepareUREMEqFold()
5652 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareUREMEqFold()
5750 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::MUL, VT)) in prepareSREMEqFold()
5905 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ADD, VT)) in prepareSREMEqFold()
5917 if (!DCI.isBeforeLegalizeOps() && !isOperationLegalOrCustom(ISD::ROTR, VT)) in prepareSREMEqFold()