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Searched refs:buildBuildVector (Results 1 – 10 of 10) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp418 B.buildBuildVector(OrigRegs[0], Regs); in buildCopyFromRegs()
435 B.buildBuildVector(OrigRegs[0], EltMerges); in buildCopyFromRegs()
440 auto BV = B.buildBuildVector(BVType, Regs); in buildCopyFromRegs()
H A DLegalizerHelper.cpp221 MIRBuilder.buildBuildVector(DstReg, PartRegs); in insertParts()
860 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalar()
2729 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); in bitcastExtractVectorElt()
3642 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorCasts()
3709 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorCmp()
3782 MIRBuilder.buildBuildVector(DstReg, DstRegs); in fewerElementsVectorSelect()
4553 Output = MIRBuilder.buildBuildVector(NarrowTy, SVOps).getReg(0); in fewerElementsVectorShuffle()
5335 MIRBuilder.buildBuildVector(DstReg, DstRegs); in narrowScalarExtract()
6744 MIRBuilder.buildBuildVector(DstReg, BuildVec); in lowerShuffleVector()
H A DIRTranslator.cpp2951 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
2962 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
2979 EntryBuilder->buildBuildVector(Reg, Ops); in translate()
H A DMachineIRBuilder.cpp632 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res, in buildBuildVector() function in MachineIRBuilder
H A DCombinerHelper.cpp239 Builder.buildBuildVector(NewDstReg, Ops); in applyCombineConcatVectors()
2902 Builder.buildBuildVector(MI.getOperand(0).getReg(), MatchInfo); in applyCombineInsertVecElts()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp2585 Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0); in legalizeAtomicCmpXChg()
3742 return B.buildBuildVector(LLT::fixed_vector(NumElts, S32), WideRegs) in handleD16VData()
3752 return B.buildBuildVector(LLT::fixed_vector(2, S32), PackedRegs) in handleD16VData()
3762 Reg = B.buildBuildVector(LLT::fixed_vector(6, S16), PackedRegs).getReg(0); in handleD16VData()
3773 return B.buildBuildVector(LLT::fixed_vector(4, S32), PackedRegs) in handleD16VData()
4188 B.buildBuildVector(V2S16, {AddrReg, B.buildUndef(S16).getReg(0)}) in packImage16bitOpsToDwords()
4192 B.buildBuildVector( in packImage16bitOpsToDwords()
4227 B.buildBuildVector(LLT::fixed_vector(NumAddrRegs, 32), AddrRegs); in convertImageAddrToPacked()
4324 auto Concat = B.buildBuildVector(PackedTy, {VData0, VData1}); in legalizeImageIntrinsic()
4603 B.buildBuildVector(DstReg, ResultRegs); in legalizeImageIntrinsic()
H A DAMDGPURegisterBankInfo.cpp986 auto Merge = B.buildBuildVector(OpTy, ReadlanePieces); in executeInWaterfallLoop()
2123 B.buildBuildVector(MI.getOperand(0), Ops); in foldInsertEltToCmpSelect()
2125 auto Vec = B.buildBuildVector(MergeTy, Ops); in foldInsertEltToCmpSelect()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h624 return MIB.buildBuildVector(NewBVTy, NewSrcs).getReg(0); in findValueFromBuildVector()
H A DMachineIRBuilder.h952 MachineInstrBuilder buildBuildVector(const DstOp &Res,
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp415 .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)}) in lowerReturn()