| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | BitTracker.h | 40 struct BitMask;
287 struct BitTracker::BitMask { struct
288 BitMask() = default;
289 BitMask(uint16_t b, uint16_t e) : B(b), E(e) {} in BitMask() argument
317 RegisterCell &insert(const RegisterCell &RC, const BitMask &M); argument
318 RegisterCell extract(const BitMask &M) const; // Returns a new cell.
465 virtual BitMask mask(unsigned Reg, unsigned Sub) const;
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| H A D | BitTracker.cpp | 216 const BitMask &M) { in insert()
236 BT::RegisterCell BT::RegisterCell::extract(const BitMask &M) const { in extract()
368 BitMask M = mask(RR.Reg, RR.Sub); in getCell()
690 RegisterCell Res = RegisterCell::ref(A1).extract(BT::BitMask(B, Last)); in eXTR()
703 Res.insert(RegisterCell::ref(A2), BT::BitMask(AtN, AtN+W2-1)); in eINS()
707 BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const { in mask()
711 return BitMask(0, W-1); in mask()
753 Res.insert(Src, BitMask(0, WS-1)); in evaluate()
1001 BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub); in subst()
1002 BitMask NM = ME.mask(NewRR.Reg, NewRR.Sub); in subst()
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| H A D | HexagonBitTracker.h | 40 BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;
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| H A D | HexagonBitTracker.cpp | 90 BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const { in mask()
102 return IsSubLo ? BT::BitMask(0, RW-1) in mask()
103 : BT::BitMask(RW, 2*RW-1); in mask()
352 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate()
374 RegisterCell CW = RegisterCell(W0).insert(rc(1), BT::BitMask(0, W1-1)); in evaluate()
724 RegisterCell RC = RegisterCell(W0).insert(Ext, BT::BitMask(0, Wd-1)); in evaluate()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | VOP3PInstructions.td | 180 class Extract<int FromBitIndex, int BitMask, bit U>: PatFrag<
182 …!if (!or (!and (!eq (BitMask, 255), !eq (FromBitIndex, 24)), !eq (FromBitIndex, 28)), // last elem…
185 !if (U, (and node:$src, (i32 BitMask)),
186 … !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src),
188 !if (U, (and (srl node:$src, (i32 FromBitIndex)), (i32 BitMask)),
189 … !if (!eq (BitMask, 15), (!cast<PatFrag>("ExtractSigned4bit_"#FromBitIndex) node:$src),
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| /freebsd-12.1/contrib/llvm/lib/Transforms/IPO/ |
| H A D | LowerTypeTests.cpp | 377 Constant *BitMask; member
527 Value *BitMask = B.CreateShl(ConstantInt::get(BitsType, 1), BitIndex); in createMaskedBitTest() local
528 Value *MaskedBits = B.CreateAnd(Bits, BitMask); in createMaskedBitTest()
625 B.CreateAnd(Byte, ConstantExpr::getPtrToInt(TIL.BitMask, Int8Ty)); in createBitSetTest()
876 ExportGlobal("bit_mask", TIL.BitMask); in exportTypeId()
878 return &TTRes.BitMask; in exportTypeId()
951 TIL.BitMask = ImportConstant("bit_mask", TTRes.BitMask, 8, Int8PtrTy); in importTypeId()
1089 TIL.BitMask = BAI->MaskGlobal; in lowerTypeTestCalls()
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| /freebsd-12.1/contrib/llvm/lib/Transforms/Utils/ |
| H A D | BypassSlowDivision.cpp | 341 uint64_t BitMask = ~BypassType->getBitMask(); in insertOperandRuntimeCheck() local
342 Value *AndV = Builder.CreateAnd(OrV, BitMask); in insertOperandRuntimeCheck()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | MachineOperand.cpp | 548 unsigned BitMask = Flags.second; in printTargetFlags() local
552 if ((BitMask & Mask.first) == Mask.first) { in printTargetFlags()
558 BitMask &= ~(Mask.first); in printTargetFlags()
561 if (BitMask) { in printTargetFlags()
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| /freebsd-12.1/contrib/llvm/include/llvm/IR/ |
| H A D | ModuleSummaryIndexYAML.h | 35 io.mapOptional("BitMask", res.BitMask);
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| H A D | ModuleSummaryIndex.h | 724 uint8_t BitMask = 0;
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| /freebsd-12.1/contrib/llvm/lib/LTO/ |
| H A D | LTO.cpp | 243 AddUint64(S.TTRes.BitMask); in computeLTOCacheKey()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1496 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy); in lowerMSABitClearImm() local
1498 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask); in lowerMSABitClearImm()
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| /freebsd-12.1/contrib/llvm/lib/IR/ |
| H A D | AsmWriter.cpp | 2754 if (TTRes.BitMask) in printTypeTestResolution()
2756 Out << ", bitMask: " << (unsigned)TTRes.BitMask; in printTypeTestResolution()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 8064 const MCExpr *BitMask; in ParseDirective() local
8067 if (Parser.parseExpression(BitMask)) { in ParseDirective()
8072 if (!BitMask->evaluateAsAbsolute(BitMaskVal)) { in ParseDirective()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 24320 SDValue BitMask = DAG.getConstant(-1, dl, ExtVT); in LowerScalarVariableShift() local
24321 BitMask = getTargetVShiftNode(LogicalX86Op, dl, ExtVT, BitMask, in LowerScalarVariableShift()
24324 BitMask = getTargetVShiftByConstNode(LogicalX86Op, dl, ExtVT, BitMask, in LowerScalarVariableShift()
24326 BitMask = DAG.getBitcast(VT, BitMask); in LowerScalarVariableShift()
24327 BitMask = DAG.getVectorShuffle(VT, dl, BitMask, BitMask, in LowerScalarVariableShift()
24334 Res = DAG.getNode(ISD::AND, dl, VT, Res, BitMask); in LowerScalarVariableShift()
31115 Res = DAG.getNode(AndOpcode, DL, MaskVT, Res, BitMask); in combineX86ShuffleChain()
36416 SDValue BitMask = N->getOperand(1); in combineAnd() local
39326 SDValue BitMask = DAG.getBuildVector(VT, DL, Bits); in combineToExtendBoolVectorInReg() local
39327 Vec = DAG.getNode(ISD::AND, DL, VT, Vec, BitMask); in combineToExtendBoolVectorInReg()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 5817 uint64_t BitMask = 0xff; in isNEONModifiedImm() local
5822 if (((SplatBits | SplatUndef) & BitMask) == BitMask) { in isNEONModifiedImm()
5823 Val |= BitMask; in isNEONModifiedImm()
5825 } else if ((SplatBits & BitMask) != 0) { in isNEONModifiedImm()
5828 BitMask <<= 8; in isNEONModifiedImm()
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| /freebsd-12.1/contrib/llvm/lib/Bitcode/Writer/ |
| H A D | BitcodeWriter.cpp | 3523 NameVals.push_back(Summary.TTRes.BitMask); in writeTypeIdSummaryRecord()
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| /freebsd-12.1/contrib/llvm/lib/Bitcode/Reader/ |
| H A D | BitcodeReader.cpp | 5220 TypeId.TTRes.BitMask = Record[Slot++]; in parseTypeIdSummaryRecord()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 9309 uint64_t BitMask = Bits == 64 ? -1ULL : ((1ULL << Bits) - 1); in tryCombineToBSL() local
9322 CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) { in tryCombineToBSL()
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| /freebsd-12.1/contrib/llvm/lib/AsmParser/ |
| H A D | LLParser.cpp | 7313 TTRes.BitMask = (uint8_t)Val; in ParseTypeTestResolution()
|