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Searched refs:caps (Results 1 – 25 of 121) sorted by relevance

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/f-stack/dpdk/drivers/net/netvsc/
H A Dhn_rndis.c576 memset(caps, 0, sizeof(*caps)); in hn_rndis_query_hwcaps()
606 caps->ndis_hdr.ndis_rev); in hn_rndis_query_hwcaps()
626 struct ndis_rss_caps in, caps; in hn_rndis_query_rsscaps() local
646 &caps, caps_len); in hn_rndis_query_rsscaps()
651 caps.ndis_nrxr, caps.ndis_nind, caps.ndis_caps); in hn_rndis_query_rsscaps()
662 caps.ndis_hdr.ndis_rev); in hn_rndis_query_rsscaps()
679 if (caps.ndis_nrxr == 0) { in hn_rndis_query_rsscaps()
683 rxr_cnt = caps.ndis_nrxr; in hn_rndis_query_rsscaps()
690 caps.ndis_nind); in hn_rndis_query_rsscaps()
696 caps.ndis_nind); in hn_rndis_query_rsscaps()
[all …]
/f-stack/freebsd/contrib/device-tree/Bindings/memory-controllers/ti/
H A Demif.txt47 - hw-caps-read-idle-ctrl: Have this property if the controller
50 - hw-caps-dll-calib-ctrl: Have this property if the controller
53 - hw-caps-ll-interface : Have this property if the controller
56 - hw-caps-temp-alert : Have this property if the controller
67 hw-caps-read-idle-ctrl;
68 hw-caps-ll-interface;
69 hw-caps-temp-alert;
/f-stack/dpdk/drivers/net/ice/base/
H A Dice_common.c1847 caps->maxtc = phys_id; in ice_parse_common_caps()
1865 caps->num_rxq); in ice_parse_common_caps()
1873 caps->num_txq); in ice_parse_common_caps()
1915 caps->maxtc = 4; in ice_recalc_port_limited_caps()
1917 caps->maxtc); in ice_recalc_port_limited_caps()
2574 cfg->caps); in ice_aq_set_phy_cfg()
2841 if (cfg.caps != pcaps->caps) { in ice_set_fc()
2903 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || in ice_phy_caps_equals_cfg()
2933 cfg->caps = caps->caps; in ice_copy_phy_caps_to_cfg()
2982 cfg->caps |= (pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC); in ice_cfg_phy_fec()
[all …]
H A Dice_common.h127 struct ice_aqc_get_phy_caps_data *caps,
144 bool ice_is_phy_caps_an_enabled(struct ice_aqc_get_phy_caps_data *caps);
146 enum ice_fc_mode ice_caps_to_fc_mode(u8 caps);
147 enum ice_fec_mode ice_caps_to_fec_mode(u8 caps, u8 fec_options);
152 ice_phy_caps_equals_cfg(struct ice_aqc_get_phy_caps_data *caps,
156 struct ice_aqc_get_phy_caps_data *caps,
/f-stack/freebsd/contrib/device-tree/Bindings/mmc/
H A Dsdhci.txt7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
10 turned off, before applying sdhci-caps.
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
/f-stack/freebsd/arm/nvidia/
H A Dtegra_sdhci.c108 u_int caps; /* If we override SDHCI_CAPABILITIES */ member
349 sc->caps = RD4(sc, SDHCI_CAPABILITIES); in tegra_sdhci_attach()
351 sc->caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); in tegra_sdhci_attach()
354 sc->caps |= MMC_CAP_8_BIT_DATA; in tegra_sdhci_attach()
357 sc->caps |= MMC_CAP_4_BIT_DATA; in tegra_sdhci_attach()
372 sc->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; in tegra_sdhci_attach()
376 sc->slot.caps = sc->caps; in tegra_sdhci_attach()
/f-stack/dpdk/drivers/vdpa/mlx5/
H A Dmlx5_vdpa_virtq.c254 if (priv->caps.queue_counters_valid) { in mlx5_vdpa_virtq_setup()
267 virtq->umems[i].size = priv->caps.umems[i].a * vq.size + in mlx5_vdpa_virtq_setup()
268 priv->caps.umems[i].b; in mlx5_vdpa_virtq_setup()
383 if (!(priv->caps.virtio_queue_type & (1 << in mlx5_vdpa_features_validate()
392 if (!priv->caps.tso_ipv4) { in mlx5_vdpa_features_validate()
400 if (!priv->caps.tso_ipv6) { in mlx5_vdpa_features_validate()
408 if (!priv->caps.tx_csum) { in mlx5_vdpa_features_validate()
416 if (!priv->caps.rx_csum) { in mlx5_vdpa_features_validate()
424 if (!priv->caps.virtio_version_1_0) { in mlx5_vdpa_features_validate()
446 if (nr_vring > priv->caps.max_num_virtio_queues * 2) { in mlx5_vdpa_virtqs_prepare()
[all …]
H A Dmlx5_vdpa.c85 *queue_num = priv->caps.max_num_virtio_queues; in mlx5_vdpa_get_queue_num()
100 if (priv->caps.virtio_queue_type & (1 << MLX5_VIRTQ_TYPE_PACKED)) in mlx5_vdpa_get_vdpa_features()
102 if (priv->caps.tso_ipv4) in mlx5_vdpa_get_vdpa_features()
104 if (priv->caps.tso_ipv6) in mlx5_vdpa_get_vdpa_features()
106 if (priv->caps.tx_csum) in mlx5_vdpa_get_vdpa_features()
108 if (priv->caps.rx_csum) in mlx5_vdpa_get_vdpa_features()
110 if (priv->caps.virtio_version_1_0) in mlx5_vdpa_get_vdpa_features()
142 if (vring >= (int)priv->caps.max_num_virtio_queues * 2) { in mlx5_vdpa_set_vring_state()
420 if (!priv->caps.queue_counters_valid) { in mlx5_vdpa_get_stats()
448 if (!priv->caps.queue_counters_valid) { in mlx5_vdpa_reset_stats()
[all …]
/f-stack/dpdk/examples/l2fwd-event/
H A Dl2fwd_event.c66 uint32_t service_id, caps; in l2fwd_event_service_setup() local
80 evt_rsrc->rx_adptr.rx_adptr[i], &caps); in l2fwd_event_service_setup()
95 evt_rsrc->tx_adptr.tx_adptr[i], &caps); in l2fwd_event_service_setup()
112 uint32_t caps = 0; in l2fwd_event_capability_setup() local
117 ret = rte_event_eth_tx_adapter_caps_get(0, i, &caps); in l2fwd_event_capability_setup()
122 evt_rsrc->tx_mode_q |= !(caps & in l2fwd_event_capability_setup()
/f-stack/dpdk/drivers/net/hns3/
H A Dhns3_cmd.c416 uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]); in hns3_parse_capability() local
418 if (hns3_get_bit(caps, HNS3_CAPS_UDP_GSO_B)) in hns3_parse_capability()
420 if (hns3_get_bit(caps, HNS3_CAPS_FD_QUEUE_REGION_B)) in hns3_parse_capability()
423 if (hns3_get_bit(caps, HNS3_CAPS_PTP_B)) in hns3_parse_capability()
425 if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B)) in hns3_parse_capability()
427 if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B)) in hns3_parse_capability()
429 if (hns3_get_bit(caps, HNS3_CAPS_TQP_TXRX_INDEP_B)) in hns3_parse_capability()
431 if (hns3_get_bit(caps, HNS3_CAPS_STASH_B)) in hns3_parse_capability()
/f-stack/dpdk/drivers/net/qede/
H A Dqede_sriov.c198 struct ecore_mcp_link_capabilities caps; in qed_inform_vf_link_state() local
209 rte_memcpy(&caps, ecore_mcp_get_link_capabilities(lead_hwfn), in qed_inform_vf_link_state()
210 sizeof(caps)); in qed_inform_vf_link_state()
215 &params, &link, &caps); in qed_inform_vf_link_state()
/f-stack/freebsd/arm/ti/
H A Dti_sdhci.c498 if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) in ti_sdhci_hw_init()
500 if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) in ti_sdhci_hw_init()
536 sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; in ti_sdhci_attach()
539 sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; in ti_sdhci_attach()
667 sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | in ti_sdhci_attach()
671 sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; in ti_sdhci_attach()
674 sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; in ti_sdhci_attach()
/f-stack/dpdk/drivers/crypto/scheduler/
H A Drte_cryptodev_scheduler.c19 sync_caps(struct rte_cryptodev_capabilities *caps, in sync_caps() argument
30 rte_memcpy(caps, worker_caps, sizeof(*caps) * nb_worker_caps); in sync_caps()
35 struct rte_cryptodev_capabilities *cap = &caps[i]; in sync_caps()
80 rte_memcpy(&caps[j], &caps[j+1], sizeof(*cap)); in sync_caps()
82 memset(&caps[sync_nb_caps - 1], 0, sizeof(*cap)); in sync_caps()
/f-stack/freebsd/x86/cpufreq/
H A Dhwpstate_intel.c374 uint64_t caps; in set_autonomous_hwp() local
411 ret = rdmsr_safe(MSR_IA32_HWP_CAPABILITIES, &caps); in set_autonomous_hwp()
423 sc->high = IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(caps); in set_autonomous_hwp()
424 sc->guaranteed = IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(caps); in set_autonomous_hwp()
425 sc->efficient = IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(caps); in set_autonomous_hwp()
426 sc->low = IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(caps); in set_autonomous_hwp()
/f-stack/dpdk/drivers/event/octeontx2/
H A Dotx2_evdev_crypto_adptr.c15 const struct rte_cryptodev *cdev, uint32_t *caps) in otx2_ca_caps_get() argument
20 *caps = RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND | in otx2_ca_caps_get()
/f-stack/dpdk/examples/l3fwd-power/
H A Dperf_core.c34 struct rte_power_core_capabilities caps; in is_hp_core() local
42 ret = rte_power_get_capabilities(lcore, &caps); in is_hp_core()
43 return ret == 0 && caps.turbo; in is_hp_core()
/f-stack/dpdk/examples/eventdev_pipeline/
H A Dpipeline_worker_generic.c562 set_worker_generic_setup_data(struct setup_data *caps, bool burst) in set_worker_generic_setup_data() argument
565 caps->worker = worker_generic_burst; in set_worker_generic_setup_data()
567 caps->worker = worker_generic; in set_worker_generic_setup_data()
570 caps->adptr_setup = init_adapters; in set_worker_generic_setup_data()
571 caps->scheduler = schedule_devices; in set_worker_generic_setup_data()
572 caps->evdev_setup = setup_eventdev_generic; in set_worker_generic_setup_data()
573 caps->check_opt = generic_opt_check; in set_worker_generic_setup_data()
H A Dpipeline_common.h143 void set_worker_generic_setup_data(struct setup_data *caps, bool burst);
144 void set_worker_tx_enq_setup_data(struct setup_data *caps, bool burst);
/f-stack/dpdk/drivers/crypto/octeontx2/
H A Dotx2_cryptodev_capabilities.c804 cpt_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps) in cpt_caps_add() argument
811 memcpy(&otx2_cpt_caps[cur_pos], caps, nb_caps * sizeof(caps[0])); in cpt_caps_add()
837 sec_caps_add(const struct rte_cryptodev_capabilities *caps, int nb_caps) in sec_caps_add() argument
844 memcpy(&otx2_cpt_sec_caps[cur_pos], caps, nb_caps * sizeof(caps[0])); in sec_caps_add()
/f-stack/dpdk/lib/librte_eventdev/
H A Drte_eventdev_pmd.h469 uint32_t *caps);
501 uint32_t *caps,
686 uint32_t *caps);
847 uint32_t *caps);
H A Drte_eventdev.c123 if (caps == NULL) in rte_event_eth_rx_adapter_caps_get()
125 *caps = 0; in rte_event_eth_rx_adapter_caps_get()
130 caps) in rte_event_eth_rx_adapter_caps_get()
144 if (caps == NULL) in rte_event_timer_adapter_caps_get()
146 *caps = 0; in rte_event_timer_adapter_caps_get()
151 caps, in rte_event_timer_adapter_caps_get()
170 if (caps == NULL) in rte_event_crypto_adapter_caps_get()
172 *caps = 0; in rte_event_crypto_adapter_caps_get()
192 if (caps == NULL) in rte_event_eth_tx_adapter_caps_get()
195 *caps = 0; in rte_event_eth_tx_adapter_caps_get()
[all …]
H A Drte_eventdev.h1152 uint32_t *caps);
1171 rte_event_timer_adapter_caps_get(uint8_t dev_id, uint32_t *caps);
1220 uint32_t *caps);
1246 uint32_t *caps);
/f-stack/dpdk/examples/l3fwd/
H A Dl3fwd_event.c174 uint32_t caps = 0; in l3fwd_event_capability_setup() local
179 ret = rte_event_eth_tx_adapter_caps_get(0, i, &caps); in l3fwd_event_capability_setup()
185 evt_rsrc->tx_mode_q |= !(caps & in l3fwd_event_capability_setup()
/f-stack/dpdk/examples/ipsec-secgw/
H A Devent_helper.c106 uint32_t caps = 0; in eh_dev_has_rx_internal_port() local
108 ret = rte_event_eth_rx_adapter_caps_get(eventdev_id, j, &caps); in eh_dev_has_rx_internal_port()
112 if (!(caps & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT)) in eh_dev_has_rx_internal_port()
125 uint32_t caps = 0; in eh_dev_has_tx_internal_port() local
127 ret = rte_event_eth_tx_adapter_caps_get(eventdev_id, j, &caps); in eh_dev_has_tx_internal_port()
131 if (!(caps & RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT)) in eh_dev_has_tx_internal_port()
327 uint32_t caps = 0; in eh_set_default_conf_rx_adapter() local
395 ret = rte_event_eth_rx_adapter_caps_get(eventdev_id, i, &caps); in eh_set_default_conf_rx_adapter()
401 if (!(caps & RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT)) in eh_set_default_conf_rx_adapter()
430 uint32_t caps = 0; in eh_set_default_conf_tx_adapter() local
[all …]
/f-stack/dpdk/drivers/event/octeontx/
H A Dssovf_evdev.c369 const struct rte_eth_dev *eth_dev, uint32_t *caps) in ssovf_eth_rx_adapter_caps_get() argument
376 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP; in ssovf_eth_rx_adapter_caps_get()
378 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT; in ssovf_eth_rx_adapter_caps_get()
552 const struct rte_eth_dev *eth_dev, uint32_t *caps) in ssovf_eth_tx_adapter_caps_get() argument
559 *caps = 0; in ssovf_eth_tx_adapter_caps_get()
561 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT; in ssovf_eth_tx_adapter_caps_get()
722 uint32_t *caps, const struct rte_event_timer_adapter_ops **ops) in ssovf_timvf_caps_get() argument
724 return timvf_timer_adapter_caps_get(dev, flags, caps, ops, in ssovf_timvf_caps_get()

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