Searched refs:GLINT_DYN_CTL_WB_ON_ITR_M (Results 1 – 2 of 2) sorted by relevance
1281 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); in ice_pf_disable_irq0()2329 GLINT_DYN_CTL_WB_ON_ITR_M); in ice_vsi_disable_queues_intr()2333 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M); in ice_vsi_disable_queues_intr()3373 GLINT_DYN_CTL_WB_ON_ITR_M); in ice_vsi_enable_queues_intr()3380 GLINT_DYN_CTL_WB_ON_ITR_M); in ice_vsi_enable_queues_intr()4519 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M; in ice_rx_queue_intr_enable()4537 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M); in ice_rx_queue_intr_disable()
4510 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30) macro