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/f-stack/dpdk/doc/guides/howto/
H A Davx512.rst5 Using AVX-512 with DPDK
8 AVX-512 is not used by default in DPDK, but it can be selected at runtime by apps through the use o…
16 Apps can request DPDK uses AVX-512 at runtime, if it provides improved application performance.
18 which does not allow for AVX-512.
31 The user can select to use AVX-512 at runtime, using the following argument to set the max bitwidth…
H A Ddebug_troubleshoot.rst277 feature_flags AVX|SSE|NEON using ``rte_cryptodev_info_get``.
/f-stack/freebsd/contrib/openzfs/lib/libspl/include/sys/
H A Dsimd.h66 AVX, enumerator
118 [AVX] = {1U, 0U, 1U << 28, ECX },
190 CPUID_FEATURE_CHECK(avx, AVX);
/f-stack/dpdk/doc/guides/compressdevs/features/
H A Disal.ini8 CPU AVX = Y
H A Ddefault.ini11 CPU AVX =
/f-stack/dpdk/doc/guides/cryptodevs/features/
H A Daesni_gcm.ini11 CPU AVX = Y
H A Daesni_mb.ini11 CPU AVX = Y
H A Ddefault.ini15 CPU AVX =
/f-stack/dpdk/drivers/net/i40e/
H A Dmeson.build32 # a. we have AVX supported in minimum instruction set baseline
/f-stack/dpdk/config/x86/
H A Dmeson.build26 'AVX',
/f-stack/dpdk/drivers/net/iavf/
H A Dmeson.build22 # a. we have AVX supported in minimum instruction set baseline
/f-stack/dpdk/drivers/net/ice/
H A Dmeson.build24 # a. we have AVX supported in minimum instruction set baseline
/f-stack/dpdk/doc/guides/rel_notes/
H A Dknown_issues.rst439 GCC might generate Intel® AVX instructions for processors without Intel® AVX support
443 When compiling DPDK (and any DPDK app), gcc may generate Intel® AVX instructions, even when the
444 processor does not support Intel® AVX.
453 Platforms which processor does not support Intel® AVX.
831 AVX-512 support disabled
835 ``AVX-512`` support has been disabled on some conditions.
837 …On DPDK v18.11 ``AVX-512`` is disabled for all ``GCC`` builds which reported to cause a performance
840 … On DPDK v19.02 ``AVX-512`` disable scope is reduced to ``GCC`` and ``binutils version 2.30`` based
844 Generated ``AVX-512`` code cause crash:
H A Drelease_19_02.rst370 * ``AVX-512`` support has been disabled for ``GCC`` builds when ``binutils 2.30``
375 Initial workaround in DPDK v18.11 was to disable ``AVX-512`` support for ``GCC``
378 generates ``AVX-512`` instructions, the scope is limited to ``GCC`` and
/f-stack/freebsd/contrib/openzfs/config/
H A Dtoolchain-simd.m4150 AC_MSG_CHECKING([whether host toolchain supports AVX])
160 AC_DEFINE([HAVE_AVX], 1, [Define if host toolchain supports AVX])
/f-stack/dpdk/lib/librte_acl/
H A Dmeson.build12 # a. we have AVX supported in minimum instruction set baseline
/f-stack/freebsd/contrib/libsodium/
H A Dconfigure.ac435 AC_MSG_CHECKING(for AVX instructions set)
438 # error NativeClient detected - Avoiding AVX opcodes
444 AC_DEFINE([HAVE_AVXINTRIN_H], [1], [AVX is available])
632 AC_MSG_CHECKING(whether we can assemble AVX opcodes)
646 AC_DEFINE([HAVE_AVX_ASM], [1], [AVX opcodes are supported])
H A DChangeLog70 AVX* when temperature/power consumption is a concern.
207 - Handle the case where the CPU supports AVX, but we are running
208 on an hypervisor with AVX disabled/not supported.
217 merged in, and is automatically used on CPUs supporting the AVX
/f-stack/freebsd/contrib/openzfs/module/icp/asm-x86_64/modes/
H A Dghash-x86_64.S71 # Broadwell 0.45(+110%)(if system doesn't support AVX)
75 # Knights L 2.12(-) (if system doesn't support AVX)
80 # ... 8x aggregate factor AVX code path is using reduction algorithm
81 # suggested by Shay Gueron[1]. Even though contemporary AVX-capable
/f-stack/dpdk/lib/librte_eal/x86/
H A Drte_cpuflags.c56 FEAT_DEF(AVX, 0x00000001, 0, RTE_REG_ECX, 28)
/f-stack/freebsd/contrib/libb2/
H A Dblake2-dispatch.c30 AVX = 4, enumerator
126 feature = AVX; in get_cpu_features()
/f-stack/dpdk/doc/guides/bbdevs/
H A Dturbo_sw.rst68 which can enable real time signal processing using AVX instructions.
/f-stack/dpdk/doc/guides/linux_gsg/
H A Deal_args.include.rst218 For example, to allow all SIMD bitwidths up to and including AVX-512::
/f-stack/dpdk/doc/guides/nics/
H A Dfm10k.rst30 SSE/AVX ''register (1)''.
H A Dixgbe.rst11 It improves load/store bandwidth efficiency of L1 data cache by using a wider SSE/AVX register 1 (1…

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