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Searched refs:ATH_READ_REG (Results 1 – 22 of 22) sorted by relevance

/f-stack/freebsd/mips/atheros/
H A Dar934x_chip.c105 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG); in ar934x_chip_detect_sys_frequency()
109 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG); in ar934x_chip_detect_sys_frequency()
117 pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG); in ar934x_chip_detect_sys_frequency()
132 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL2_REG); in ar934x_chip_detect_sys_frequency()
136 pll = ATH_READ_REG(AR934X_SRIF_DDR_DPLL1_REG); in ar934x_chip_detect_sys_frequency()
144 pll = ATH_READ_REG(AR934X_PLL_DDR_CONFIG_REG); in ar934x_chip_detect_sys_frequency()
212 reg = ATH_READ_REG(AR934X_RESET_REG_RESET_MODULE); in ar934x_chip_device_stop()
330 reg = ATH_READ_REG(AR934X_GMAC_REG_ETH_CFG); in ar934x_configure_gmac()
347 reg = ATH_READ_REG(AR934X_RESET_REG_BOOTSTRAP); in ar934x_chip_init_usb_peripheral()
449 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg); in ar934x_chip_gpio_output_configure()
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H A Dqca953x_chip.c80 bootstrap = ATH_READ_REG(QCA953X_RESET_REG_BOOTSTRAP); in qca953x_chip_detect_sys_frequency()
86 pll = ATH_READ_REG(QCA953X_PLL_CPU_CONFIG_REG); in qca953x_chip_detect_sys_frequency()
100 pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG); in qca953x_chip_detect_sys_frequency()
114 clk_ctrl = ATH_READ_REG(QCA953X_PLL_CLK_CTRL_REG); in qca953x_chip_detect_sys_frequency()
161 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE); in qca953x_chip_device_stop()
170 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE); in qca953x_chip_device_start()
179 reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE); in qca953x_chip_device_stopped()
265 reg = ATH_READ_REG(QCA953X_GMAC_REG_ETH_CFG); in qca953x_configure_gmac()
281 bootstrap = ATH_READ_REG(QCA953X_RESET_REG_BOOTSTRAP); in qca953x_chip_init_usb_peripheral()
367 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg); in qca953x_chip_gpio_output_configure()
[all …]
H A Dqca955x_chip.c81 bootstrap = ATH_READ_REG(QCA955X_RESET_REG_BOOTSTRAP); in qca955x_chip_detect_sys_frequency()
87 pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG); in qca955x_chip_detect_sys_frequency()
101 pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG); in qca955x_chip_detect_sys_frequency()
115 clk_ctrl = ATH_READ_REG(QCA955X_PLL_CLK_CTRL_REG); in qca955x_chip_detect_sys_frequency()
162 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE); in qca955x_chip_device_stop()
171 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE); in qca955x_chip_device_start()
180 reg = ATH_READ_REG(QCA955X_RESET_REG_RESET_MODULE); in qca955x_chip_device_stopped()
278 reg = ATH_READ_REG(QCA955X_GMAC_REG_ETH_CFG); in qca955x_configure_gmac()
376 t = ATH_READ_REG(AR71XX_GPIO_BASE + reg); in qca955x_chip_gpio_output_configure()
382 ATH_READ_REG(AR71XX_GPIO_BASE + reg); in qca955x_chip_gpio_output_configure()
H A Dar933x_chip.c78 t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP); in ar933x_chip_detect_sys_frequency()
84 clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG); in ar933x_chip_detect_sys_frequency()
90 cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG); in ar933x_chip_detect_sys_frequency()
144 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); in ar933x_chip_device_stop()
153 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); in ar933x_chip_device_start()
162 reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE); in ar933x_chip_device_stopped()
258 reg = ATH_READ_REG(AR933X_GMAC_REG_ETH_CFG); in ar933x_configure_gmac()
H A Dar71xx_chip.c100 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_chip_detect_sys_frequency()
125 reg = ATH_READ_REG(AR71XX_RST_RESET); in ar71xx_chip_device_stop()
134 reg = ATH_READ_REG(AR71XX_RST_RESET); in ar71xx_chip_device_start()
143 reg = ATH_READ_REG(AR71XX_RST_RESET); in ar71xx_chip_device_stopped()
181 val = ATH_READ_REG(reg); in ar71xx_chip_set_mii_speed()
227 val = ATH_READ_REG(reg); in ar71xx_chip_set_mii_if()
H A Dqca955x_pci.c124 val = ATH_READ_REG(reg + (offset & ~3)); in qca955x_pci_write()
155 data = ATH_READ_REG(sc->sc_pci_reg_base + (reg & ~3)); in qca955x_pci_read_config()
194 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK); in qca955x_pci_mask_irq()
199 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS); in qca955x_pci_mask_irq()
215 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK); in qca955x_pci_unmask_irq()
236 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET); in qca955x_pci_setup()
240 ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET); in qca955x_pci_setup()
243 ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET); in qca955x_pci_setup()
249 (void) ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_APP); in qca955x_pci_setup()
253 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET); in qca955x_pci_setup()
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H A Dar91xx_chip.c76 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG); in ar91xx_chip_detect_sys_frequency()
96 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); in ar91xx_chip_device_stop()
105 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); in ar91xx_chip_device_start()
114 reg = ATH_READ_REG(AR91XX_RESET_REG_RESET_MODULE); in ar91xx_chip_device_stopped()
H A Dar724x_chip.c78 pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); in ar724x_chip_detect_sys_frequency()
103 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); in ar724x_chip_device_stop()
115 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); in ar724x_chip_device_start()
126 reg = ATH_READ_REG(AR724X_RESET_REG_RESET_MODULE); in ar724x_chip_device_stopped()
H A Dar724x_pci.c110 val = ATH_READ_REG(reg + (offset & ~3)); in ar724x_pci_write()
142 data = ATH_READ_REG(AR724X_PCI_CFG_BASE + (reg & ~3)); in ar724x_pci_read_config()
197 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK); in ar724x_pci_mask_irq()
202 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS); in ar724x_pci_mask_irq()
218 reg = ATH_READ_REG(AR724X_PCI_INTR_MASK); in ar724x_pci_unmask_irq()
236 reg = ATH_READ_REG(AR724X_PCI_RESET); in ar724x_pci_setup()
251 (void) ATH_READ_REG(AR724X_PCI_APP); in ar724x_pci_setup()
255 reg = ATH_READ_REG(AR724X_PCI_RESET); in ar724x_pci_setup()
263 reg = ATH_READ_REG(AR724X_PCI_APP); in ar724x_pci_setup()
597 reg = ATH_READ_REG(AR724X_PCI_INTR_STATUS); in ar724x_pci_intr()
[all …]
H A Dar71xx_pci.c108 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); in ar71xx_pci_mask_irq()
110 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); in ar71xx_pci_mask_irq()
121 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); in ar71xx_pci_unmask_irq()
124 reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK); in ar71xx_pci_unmask_irq()
156 error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3; in ar71xx_pci_check_bus_error()
159 addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR); in ar71xx_pci_check_bus_error()
169 error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1; in ar71xx_pci_check_bus_error()
172 addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR); in ar71xx_pci_check_bus_error()
237 data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA); in ar71xx_pci_read_config()
623 reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS); in ar71xx_pci_intr()
[all …]
H A Dar71xxreg.h532 #define ATH_READ_REG(reg) \ macro
546 while ((ATH_READ_REG(reg) & 0x1)) in ar71xx_ddr_flush()
549 while ((ATH_READ_REG(reg) & 0x1)) in ar71xx_ddr_flush()
559 sec_cfg = ATH_READ_REG(cfg_reg); in ar71xx_write_pll()
H A Duart_bus_ar71xx.c98 if (ATH_READ_REG(AR71XX_UART_ADDR + AR71XX_UART_LSR) in ar71xx_early_putc()
H A Duart_bus_ar933x.c106 while ((i > 0) && (ATH_READ_REG(AR71XX_UART_ADDR + AR933X_UART_CS_REG) & in ar933x_early_putc()
H A Dapb.c91 reg = ATH_READ_REG(AR71XX_MISC_INTR_MASK); in apb_mask_irq()
102 reg = ATH_READ_REG(AR71XX_MISC_INTR_MASK); in apb_unmask_irq()
356 reg = ATH_READ_REG(AR71XX_MISC_INTR_STATUS); in apb_filter()
H A Dar71xx_setup.c89 id = ATH_READ_REG(AR71XX_RST_RESET_REG_REV_ID); in ar71xx_detect_sys_type()
H A Dar71xx_wdog.c156 if (ATH_READ_REG(AR71XX_RST_WDOG_CONTROL) & RST_WDOG_LAST) { in ar71xx_wdog_attach()
/f-stack/freebsd/mips/atheros/ar531x/
H A Dar5312_chip.c73 memcfg = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1); in ar5312_chip_detect_mem_size()
90 const uint32_t clockctl = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_CLOCKCTL); in ar5312_chip_detect_sys_frequency()
125 cfg0 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG0); in ar5312_chip_device_start()
126 cfg1 = ATH_READ_REG(AR5312_SDRAMCTL_BASE + AR5312_SDRAMCTL_MEM_CFG1); in ar5312_chip_device_start()
139 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBPERR); in ar5312_chip_device_start()
140 ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_AHBDMAE); in ar5312_chip_device_start()
145 ATH_READ_REG(AR5312_SYSREG_BASE+AR5312_SYSREG_ENABLE) | in ar5312_chip_device_start()
155 reg = ATH_READ_REG(AR5312_SYSREG_BASE + AR5312_SYSREG_RESETCTL); in ar5312_chip_device_stopped()
H A Dar5315_chip.c85 memcfg = ATH_READ_REG(AR5315_SDRAMCTL_BASE + AR5315_SDRAMCTL_MEM_CFG); in ar5315_chip_detect_mem_size()
121 const uint32_t pllc = ATH_READ_REG(AR5315_SYSREG_BASE + in ar5315_chip_detect_sys_frequency()
145 const uint32_t amba_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE + in ar5315_chip_detect_sys_frequency()
151 const uint32_t cpu_clkctl = ATH_READ_REG(AR5315_SYSREG_BASE + in ar5315_chip_detect_sys_frequency()
175 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ERR1); in ar5315_chip_device_start()
182 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL) | in ar5315_chip_device_start()
195 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_AHB_ARB_CTL)); in ar5315_chip_device_start()
197 ATH_READ_REG(AR5315_SYSREG_BASE+AR5315_SYSREG_ENDIAN)); in ar5315_chip_device_start()
205 reg = ATH_READ_REG(AR5315_SYSREG_BASE + AR5315_SYSREG_COLDRESET); in ar5315_chip_device_stopped()
H A Dapb.c102 reg = ATH_READ_REG(AR5315_SYSREG_BASE + in apb_mask_irq()
107 reg = ATH_READ_REG(AR5312_SYSREG_BASE + in apb_mask_irq()
121 reg = ATH_READ_REG(AR5315_SYSREG_BASE + in apb_unmask_irq()
126 reg = ATH_READ_REG(AR5312_SYSREG_BASE + in apb_unmask_irq()
489 reg = ATH_READ_REG(AR5315_SYSREG_BASE + in apb_filter()
492 reg = ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()
510 ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()
512 ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()
553 ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()
555 ATH_READ_REG(AR5312_SYSREG_BASE + in apb_filter()
[all …]
H A Dar5315_setup.c109 ver = ATH_READ_REG(AR5315_SYSREG_BASE + in ar5315_detect_sys_type()
133 ver = ATH_READ_REG(AR5312_SYSREG_BASE + in ar5315_detect_sys_type()
H A Dar5315reg.h224 #define ATH_READ_REG(reg) \ macro
H A Dar5315_spi.c146 *((uint32_t *)data + i) = ATH_READ_REG(AR5315_MEM1_BASE + offset + i * 4); in ar5315_spi_get_block()