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Searched refs:GENMASK_ULL (Results 1 – 16 of 16) sorted by relevance

/dpdk/drivers/common/cnxk/
H A Droc_bphy_cgx_priv.h101 #define SCR0_ETH_EVT_STS_S_ID GENMASK_ULL(8, 3)
106 #define SCR0_ETH_LNK_STS_S_SPEED GENMASK_ULL(14, 11)
107 #define SCR0_ETH_LNK_STS_S_ERR_TYPE GENMASK_ULL(24, 15)
109 #define SCR0_ETH_LNK_STS_S_FEC GENMASK_ULL(27, 26)
110 #define SCR0_ETH_LNK_STS_S_LMAC_TYPE GENMASK_ULL(35, 28)
111 #define SCR0_ETH_LNK_STS_S_MODE GENMASK_ULL(43, 36)
114 #define SCR0_ETH_FEC_TYPES_S_FEC GENMASK_ULL(10, 9)
121 #define SCR1_ETH_CMD_ID GENMASK_ULL(7, 2)
127 #define SCR1_ETH_MODE_CHANGE_ARGS_SPEED GENMASK_ULL(11, 8)
134 #define SCR1_ETH_SET_FEC_ARGS GENMASK_ULL(9, 8)
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H A Droc_bits.h26 #ifndef GENMASK_ULL
27 #define GENMASK_ULL(h, l) \ macro
H A Droc_bphy_cgx.c25 #define CGX_CMRX_RX_LMACS_LMACS GENMASK_ULL(3, 0)
173 uint64_t cgx_id = roc_model_is_cn10k() ? GENMASK_ULL(26, 24) : in roc_bphy_cgx_dev_id()
174 GENMASK_ULL(25, 24); in roc_bphy_cgx_dev_id()
195 val = GENMASK_ULL(val - 1, 0); in roc_bphy_cgx_dev_init()
H A Droc_nix_tm_utils.c563 regval_mask[k] = ~(BIT_ULL(50) | GENMASK_ULL(6, 0) | in nix_tm_topology_reg_prep()
564 GENMASK_ULL(23, 8) | GENMASK_ULL(38, 36)); in nix_tm_topology_reg_prep()
H A Droc_platform.h57 #define BITMASK_ULL GENMASK_ULL
H A Droc_nix_tm.c375 req->regval_mask[k] = ~(BIT_ULL(13) | GENMASK_ULL(7, 0)); in nix_tm_bp_config_set()
/dpdk/drivers/raw/ifpga/base/
H A Dopae_spi.h34 #define CTRL_ADDR_MASK GENMASK_ULL(2, 0)
37 #define READ_DATA_MASK GENMASK_ULL(31, 0)
39 #define WRITE_DATA_MASK GENMASK_ULL(31, 0)
144 #define PERI_ID GENMASK_ULL(47, 32)
145 #define SPI_CLK GENMASK_ULL(31, 22)
146 #define SYNC_STAGES GENMASK_ULL(17, 16)
149 #define NUM_SELECT GENMASK_ULL(13, 8)
150 #define DATA_WIDTH GENMASK_ULL(7, 2)
156 #define NIOS_SPI_COMMAND GENMASK_ULL(63, 62)
157 #define NIOS_SPI_ADDR GENMASK_ULL(44, 32)
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H A Dopae_eth_group.h22 #define INFO_SPEED GENMASK_ULL(23, 16)
25 #define INFO_PHY_NUM GENMASK_ULL(15, 8)
26 #define INFO_GROUP_NUM GENMASK_ULL(7, 0)
29 #define CTRL_CMD GENMASK_ULL(63, 62)
34 #define CTRL_DEV_SELECT GENMASK_ULL(53, 49)
39 #define CTRL_ADDR GENMASK_ULL(47, 32)
41 #define CTRL_WR_DATA GENMASK_ULL(31, 0)
45 #define STAT_RD_DATA GENMASK_ULL(31, 0)
H A Dopae_i2c.h52 #define I2C_CTRL_ADDR_MASK GENMASK_ULL(3, 0)
55 #define I2C_READ_DATA_MASK GENMASK_ULL(31, 0)
57 #define I2C_WRITE_DATA_MASK GENMASK_ULL(31, 0)
H A Dopae_osdep.h47 #ifndef GENMASK_ULL
48 #define GENMASK_ULL(h, l) \ macro
/dpdk/drivers/net/nfp/nfpcore/
H A Dnfp_nsp.h12 #define GENMASK_ULL(h, l) \ macro
38 #define NSP_STATUS_MAGIC GENMASK_ULL(63, 48)
39 #define NSP_STATUS_MAJOR GENMASK_ULL(47, 44)
40 #define NSP_STATUS_MINOR GENMASK_ULL(43, 32)
41 #define NSP_STATUS_CODE GENMASK_ULL(31, 16)
42 #define NSP_STATUS_RESULT GENMASK_ULL(15, 8)
46 #define NSP_COMMAND_OPTION GENMASK_ULL(63, 32)
47 #define NSP_COMMAND_CODE GENMASK_ULL(31, 16)
52 #define NSP_BUFFER_CPP GENMASK_ULL(63, 40)
53 #define NSP_BUFFER_PCIE GENMASK_ULL(39, 38)
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H A Dnfp_nsp_eth.c13 #define GENMASK_ULL(h, l) \ macro
42 #define NSP_ETH_PORT_LANES GENMASK_ULL(3, 0)
43 #define NSP_ETH_PORT_INDEX GENMASK_ULL(15, 8)
44 #define NSP_ETH_PORT_LABEL GENMASK_ULL(53, 48)
45 #define NSP_ETH_PORT_PHYLABEL GENMASK_ULL(59, 54)
55 #define NSP_ETH_STATE_RATE GENMASK_ULL(11, 8)
56 #define NSP_ETH_STATE_INTERFACE GENMASK_ULL(19, 12)
57 #define NSP_ETH_STATE_MEDIA GENMASK_ULL(21, 20)
59 #define NSP_ETH_STATE_ANEG GENMASK_ULL(25, 23)
60 #define NSP_ETH_STATE_FEC GENMASK_ULL(27, 26)
/dpdk/drivers/common/cnxk/hw/
H A Dree.h56 #define REE_LF_SBUF_ADDR_OFF_MASK GENMASK_ULL(6, 0)
57 #define REE_LF_SBUF_ADDR_PTR_MASK GENMASK_ULL(52, 7)
/dpdk/drivers/net/ena/base/
H A Dena_eth_com.c521 GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); in ena_com_prepare_tx()
643 ((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32); in ena_com_add_single_rx_desc()
H A Dena_plat_dpdk.h112 #define GENMASK_ULL(h, l) (((~0ULL) - (1ULL << (l)) + 1) & \ macro
H A Dena_com.c72 if ((addr & GENMASK_ULL(ena_dev->dma_addr_bits - 1, 0)) != addr) { in ena_com_mem_addr_set()