Searched refs:CSR (Results 1 – 4 of 4) sorted by relevance
| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/ |
| H A D | inst.isle | 75 (csr CSR))
82 (csr CSR))
730 ;; Atomic Read/Write CSR
732 ;; Atomic Read and Set Bits in CSR
734 ;; Atomic Read and Clear Bits in CSR
747 ;; Enum of the known CSR registers
748 (type CSR (enum
1822 (decl rv_csrrwi (CSR UImm5) XReg)
1826 ;; This is a special case of `csrrwi` when the CSR is the `frm` CSR.
1833 (decl rv_csrw (CSR XReg) Unit)
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| /wasmtime-44.0.1/cranelift/codegen/src/isa/riscv64/inst/ |
| H A D | encode.rs | 310 pub fn encode_csr_reg(op: CsrRegOP, rd: WritableReg, rs: Reg, csr: CSR) -> u32 { in encode_csr_reg()
316 pub fn encode_csr_imm(op: CsrImmOP, rd: WritableReg, csr: CSR, imm: UImm5) -> u32 { in encode_csr_imm() argument
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| H A D | args.rs | 1669 impl CSR { impl
1672 CSR::Frm => 0x0002, in bits()
1678 CSR::Frm => "frm", in name()
1683 impl Display for CSR { implementation
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| H A D | mod.rs | 49 AluOPRRI, AluOPRRR, AtomicOP, CSR, CsrImmOP, CsrRegOP, FClassResult, FFlagsException, FRM,
1265 (CsrRegOP::CsrRW, CSR::Frm, rd) if rd.to_reg() == zero_reg() => { in print_with_state()
1277 (CsrImmOP::CsrRWI, CSR::Frm, rd) if rd.to_reg() != zero_reg() => { in print_with_state()
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