Add inital support for `f16` without `Zfh` and `f128` to the riscv64 backend (#10652)

riscv64: Refactor Floating Point Instruction Emission (#9084)

* riscv64: Refactor FpuRR instruction emission

Previously we had opcodes for each instruction length variant, with the width field impl

riscv64: Refactor Floating Point Instruction Emission (#9084)

* riscv64: Refactor FpuRR instruction emission

Previously we had opcodes for each instruction length variant, with the width field implicitly embedded in the `funct7` field of the opcode.

This works, but the instructions are defined with the width field having a few more possible values. In order to add FP16 support to these instructions we would have to duplicate the opcodes.

Instead make these opcodes width agnostic and specifiy the width during emission.

* riscv64: Refactor FpuRRR instruction emission

Previously we had opcodes for each instruction length variant, with the width field implicitly embedded in the `funct7` field of the opcode.

This works, but the instructions are defined with the width field having a few more possible values. In order to add FP16 support to these instructions we would have to duplicate the opcodes.

Instead make these opcodes width agnostic and specifiy the width during emission.

* riscv64: Refactor FpuRRRR instruction emission

Previously we had opcodes for each instruction length variant, with the width field implicitly embedded in the `funct7` field of the opcode.

This works, but the instructions are defined with the width field having a few more possible values. In order to add FP16 support to these instructions we would have to duplicate the opcodes.

Instead make these opcodes width agnostic and specifiy the width during emission.

* riscv64: Fix emit tests

* riscv64: Run `cargo fmt`

show more ...

Fix some typos (#8641)

* occurred

* winch typos

* tests typos

* cli typos

* fuzz typos

* examples typos

* docs typos

* crates/wasmtime typos

* crates/environ typos

* crates/cranelift typos

Fix some typos (#8641)

* occurred

* winch typos

* tests typos

* cli typos

* fuzz typos

* examples typos

* docs typos

* crates/wasmtime typos

* crates/environ typos

* crates/cranelift typos

* crates/test-programs typos

* crates/c-api typos

* crates/cache typos

* crates other typos

* cranelift/codegen/src/isa typos

* cranelift/codegen/src other typos

* cranelift/codegen other typos

* cranelift other typos

* ci js typo

* .github workflows typo

* RELEASES typo

* Fix clang-format documentation line

---------

Co-authored-by: Andrew Brown <[email protected]>

show more ...

riscv64: Add remaining Zfa Instructions (#8582)

* riscv64: Add `fround` instruction

* riscv64: Remove unused load_fp functions

* riscv64: Add support for `fli` instruction

* riscv64: Add negated

riscv64: Add remaining Zfa Instructions (#8582)

* riscv64: Add `fround` instruction

* riscv64: Remove unused load_fp functions

* riscv64: Add support for `fli` instruction

* riscv64: Add negated `fli` rules

show more ...

Fix rustdoc warnings on Nightly (#8258)

* Fix rustdoc warnings on Nightly

I noticed during a failed doc build of another PR we've got a number of
warnings being emitted, so resolve all those here.

Fix rustdoc warnings on Nightly (#8258)

* Fix rustdoc warnings on Nightly

I noticed during a failed doc build of another PR we've got a number of
warnings being emitted, so resolve all those here.

* Fix more warnings

* Fix rebase conflicts

show more ...

Update some CI dependencies (#7983)

* Update some CI dependencies

* Update to the latest nightly toolchain
* Update mdbook
* Update QEMU for cross-compiled testing
* Update `cargo nextest` for usag

Update some CI dependencies (#7983)

* Update some CI dependencies

* Update to the latest nightly toolchain
* Update mdbook
* Update QEMU for cross-compiled testing
* Update `cargo nextest` for usage with MIRI

prtest:full

* Remove lots of unnecessary imports

* Downgrade qemu as 8.2.1 seems to segfault

* Remove more imports

* Remove unused winch trait method

* Fix warnings about unused trait methods

* More unused imports

* More unused imports

show more ...

riscv64: Fix encoding for `c.addi4spn` (#7208)

* riscv64: Fix encoding for `c.addi4spn`

* riscv64: Add a few more `c.addi4spn` tests

riscv64: Add `Zcb` extension instructions (#7123)

* riscv64: Add `c.mul`

* riscv64: Add `c.not`

* riscv64: Add zbb and zba dependent compressed instructions

* riscv64: Add `Zcb` loads and stores

riscv64: Add `Zcb` extension instructions (#7123)

* riscv64: Add `c.mul`

* riscv64: Add `c.not`

* riscv64: Add zbb and zba dependent compressed instructions

* riscv64: Add `Zcb` loads and stores

* riscv64: Restrict immediate encoding for halfword compressed stores and loads

* riscv64: Reverse imm bits for bytewise compressed loads and stores

show more ...

riscv64: Add the remainder of Zca and Zcd instructions (#7080)

* riscv64: Add `c.li` and `c.lui`

* riscv64: Add CB type instructions

`c.srli` / `c.srai` / `c.andi`

* riscv64: Add `sp` relative lo

riscv64: Add the remainder of Zca and Zcd instructions (#7080)

* riscv64: Add `c.li` and `c.lui`

* riscv64: Add CB type instructions

`c.srli` / `c.srai` / `c.andi`

* riscv64: Add `sp` relative load instructions

* riscv64: Return Option from try_emit_compressed

* riscv64: Implement stack based stores

* riscv64: Add compressed stores

* riscv64: Add compressed loads

show more ...

riscv64: Add compressed `addi` (#7057)

* riscv64: Add `c.ebreak` instruction

* riscv64: Implement `c.unimp`

* riscv64: Add `c.addi`

* riscv64: Add `c.addiw`

* riscv64: Add `c.addi16sp`

* riscv6

riscv64: Add compressed `addi` (#7057)

* riscv64: Add `c.ebreak` instruction

* riscv64: Implement `c.unimp`

* riscv64: Add `c.addi`

* riscv64: Add `c.addiw`

* riscv64: Add `c.addi16sp`

* riscv64: Add `c.slli`

* riscv64: Add `c.addi4spn`

* riscv64: Update `c.addiw` comment

* riscv64: Centralize Zca Check

* riscv64: Avoid double construction in some match arms

show more ...

riscv64: Refactor how immediates are stored and used (#7045)

I was curious to poke around the riscv64 backend and I wanted to touch
up the handling of `Imm{12,20}` a bit after reading it. This commi

riscv64: Refactor how immediates are stored and used (#7045)

I was curious to poke around the riscv64 backend and I wanted to touch
up the handling of `Imm{12,20}` a bit after reading it. This commit is a
refactoring of these two types with the following changes:

* The payload of these types is now unsigned and guarantees that
irrelevant bits are set to zero. For example `Imm12` is stored as
`u16` where the upper four bits are guaranteed to be zero. This fixes
a discrepancy where `Imm12::maybe_from_i64` was masked for example but
`Imm12::from_bits` wasn't.

* The `Neg for Imm12` impl was removed because -2048 is a valid
`Imm12` but 2048 is not in-range for `Imm12` meaning that it is not an
infallible operation.

* Accessors are now named `bits` to get the `u32` representation
suitable to be encoded into an instruction. Acquiring the underlying
value is now done with `as_i{16,32}` depending on the type. The signed
accessor does sign-extension as required to produce the semantically
equivalent value.

* Manual constructors were renamed to `from_{i16,i32}` instead of
`from_bits`. This in theory helps convey that they're constructors for
logical values rather than literal bit-wise values. Additionally
asserts are now placed in these constructors asserting that the
provided value is in-range.

* The `FALSE` and `TRUE` constants were renamed `ZERO` and `ONE` and
`Imm20::ZERO` was added.

This commit ended up changing many runtests, but only their CLIF
printing rather than their encoding. This change is due to the fact that
`Display` now prints the logical value of the immediate rather than the
raw bit representation as a base 10 integer. It's not intended that this
commit actually changes any behavior, instead it should purely be
internal refactorings.

show more ...

riscv64: Add more compressed instructions (#7030)

* riscv64: Update funct4 field width on CR type

It's only 4 bits, not 5

* riscv64: Add CA Ops

* riscv64: Encode `c.j` instructions

* riscv64: Us

riscv64: Add more compressed instructions (#7030)

* riscv64: Update funct4 field width on CR type

It's only 4 bits, not 5

* riscv64: Add CA Ops

* riscv64: Encode `c.j` instructions

* riscv64: Use uncompressed instructions where labels are used.

Not doing so could cause a compressed instruction to be emitted with the wrong label type.

* riscv64: Implement `c.jr` instruction

* riscv64: Implement `c.jalr` instruction

This also update CallIndirect to allow compressing Jalr

* riscv64: Update RVCJump label range

It is only +-2KiB instead of +-4KiB

show more ...

riscv64: Introduce Compressed Instructions (#6989)

* riscv64: Add compressed extension instructions

The C extension has been split a little bit since its introduction
let's support the finer graine

riscv64: Introduce Compressed Instructions (#6989)

* riscv64: Add compressed extension instructions

The C extension has been split a little bit since its introduction
let's support the finer grained instructions.

This also disables compressed instruction support by default.

* ci: Enable zcb extension on RISC-V QEMU

* riscv64: Enable RVC mode in capstone

Conditionally enable compressed instruction disassembly.

* riscv64: Prepare to emit compressed instructions

This commit reorganizes our emit function to first
try a special case for compressed instruction, before
falling back to uncompressed instructions.

Currently the compressed case does nothing.

* riscv64: Move emit register allocation to separate function

We can only emit compressed instructions if they have a
specific physical register. For example `c.mv` does not support
using the `x0` register.

Thus, move the allocation function that converts from
virtual registers to physical registers into a separate step
before trying to emit the instruction.

This allows us to know the real register when emitting
compressed instructions.

* riscv64: Emit BrTable as uncompressed

`br_table` computes physical offsets from a certain instruction.
Thus we need to force these instructions to be uncompressed
in order to not jump into the wrong target.

* riscv64: Mark DWARF CIE code alignment as 2 bytes

* riscv64: Make minimum function alignment 2 bytes

* riscv64: Emit `c.add`

* riscv64: Add `c.mv`

* riscv64: Add c runtests

* Revert "ci: Enable zcb extension on RISC-V QEMU"

This reverts commit 212dec48d4ef0ab2d92ad55e3a649b914ca0fb39.

It looks like the version of QEMU that CI uses does not yet
support Zcb.

show more ...

riscv64: Implement vector floating point rounding instructions (#6920)

* riscv64: Add CSR Instructions

* riscv64: Add float to int vector instructions

* cranelift: Split vector rounding mode tests

riscv64: Implement vector floating point rounding instructions (#6920)

* riscv64: Add CSR Instructions

* riscv64: Add float to int vector instructions

* cranelift: Split vector rounding mode tests

* riscv64: Implement float rounding ops for vectors

* riscv64: Update tests

show more ...

riscv64: Add IFMA instruction support (#6815)

riscv64: Implement `iadd_pairwise` (#6568)

* riscv64: Add Mov and VSlideUp

* riscv64: Implement `iadd_pairwise`

* riscv64: Use `late_use` in `VecAluRRRImm5`

* machinst: Add `OperandCollector::reg

riscv64: Implement `iadd_pairwise` (#6568)

* riscv64: Add Mov and VSlideUp

* riscv64: Implement `iadd_pairwise`

* riscv64: Use `late_use` in `VecAluRRRImm5`

* machinst: Add `OperandCollector::reg_fixed_late_use`

show more ...

riscv64: Add `extractlane` and `splat` instructions (#6397)

* riscv64: Add `vslidedown.v{x,i}` instructions

* riscv64: Add `v{f,}mv` instructions

These instructions move values from vectors into o

riscv64: Add `extractlane` and `splat` instructions (#6397)

* riscv64: Add `vslidedown.v{x,i}` instructions

* riscv64: Add `v{f,}mv` instructions

These instructions move values from vectors into other register types and vice-versa.

* riscv64: Add `extractlane` lowerings

* riscv64: Add `vmv.v.*` instructions

* riscv64: Implement `splat`

* riscv64: Add `vmv.v.i` instruction

* riscv64: Remove unused `imm5_zero`

* wasmtime: Enable more RISC-V SIMD tests

* cranelift: Enable ssse3 tests for `fadd-splat` testsuite

* riscv64: Update splat TODO comment

show more ...

riscv64: Add `vconst` lowerings (#6324)

* riscv64: Use `LoadAddr` on `Load`/`Store`

* riscv64: Add I Type encoding

* riscv64: Add S Type encoding

* riscv64: Use `LoadAddr` on `VecLoad`/`VecStore`

riscv64: Add `vconst` lowerings (#6324)

* riscv64: Use `LoadAddr` on `Load`/`Store`

* riscv64: Add I Type encoding

* riscv64: Add S Type encoding

* riscv64: Use `LoadAddr` on `VecLoad`/`VecStore`

* riscv64: Add Const/Lable AModes

* riscv64: Add Label Address Generation

* riscv64: Add `vconst` support

* riscv64: Use `unsigned_field_width` in encode

* riscv64: Use `WritableReg` in encode

* riscv64: Deduplicate AMode formatting

* riscv64: Refcator VectorLoad/Store AMode Pattern matching

* riscv64: Avoid passing `fp` and `sp` through the register allocator

* riscv64: Fix `PCRel{Hi20,Lo12I}` relocation

* riscv64: Update PCRelLo12I Comment

show more ...

riscv64: Add `VecALUImm` instruction format (#6325)

* riscv64: Add `VecALUImm` instruction format

* riscv64: Add VecOpCategory struct

* riscv64: Fix `imm5_from_u64`

* riscv64: Improve instruction

riscv64: Add `VecALUImm` instruction format (#6325)

* riscv64: Add `VecALUImm` instruction format

* riscv64: Add VecOpCategory struct

* riscv64: Fix `imm5_from_u64`

* riscv64: Improve instruction encoding type safety

* riscv64: Run rustfmt

* riscv64: Use `VecOpCategory` in `vcfg` encoding

show more ...

riscv64: Implement a few SIMD arithmetic ops (#6268)

* riscv64: Swap order of `VecAluRRR` source registers

These were accidentally reversed from what we declare in the isle emit helper

* riscv64:

riscv64: Implement a few SIMD arithmetic ops (#6268)

* riscv64: Swap order of `VecAluRRR` source registers

These were accidentally reversed from what we declare in the isle emit helper

* riscv64: Add SIMD `isub`

* riscv64: Add SIMD `imul`

* riscv64: Add `{u,s}mulhi`

* riscv64: Add `b{and,or,xor}`

* cranelift: Move `imul.i8x16` runtest to separate file

Looks like x86 does not implement it

* riscv64: Better formatting for `VecAluOpRRR`

* cranelift: Enable x86 SIMD tests with `has_sse41=false`

show more ...

riscv64: Initial SIMD Vector Implementation (#6240)

* riscv64: Remove unused code

* riscv64: Add vector types

* riscv64: Initial Vector ABI Load/Stores

* riscv64: Vector Loads/Stores

* riscv64:

riscv64: Initial SIMD Vector Implementation (#6240)

* riscv64: Remove unused code

* riscv64: Add vector types

* riscv64: Initial Vector ABI Load/Stores

* riscv64: Vector Loads/Stores

* riscv64: Fix `vsetvli` encoding error

* riscv64: Add SIMD `iadd` runtests

* riscv64: Rename `VecSew`

The SEW name is correct, but only for VType. We also use this type
in loads/stores as the Efective Element Width, so the name isn't
quite correct in that case.

* ci: Add V extension to RISC-V QEMU

* riscv64: Misc Cleanups

* riscv64: Check V extension in `load`/`store` for SIMD

* riscv64: Fix `sumop` doc comment

* cranelift: Fix comment typo

* riscv64: Add convert for VType and VecElementWidth

* riscv64: Remove VecElementWidth converter

show more ...