| /wasmtime-44.0.1/cranelift/isle/isle/isle_examples/pass/ |
| H A D | tutorial.isle | 5 (enum (Add (a Value) (b Value))
15 (enum (Add (mode AddrMode))
51 (rule -1 (lower (HighLevelInst.Add a b))
52 (LowLevelInst.Add
66 (LowLevelInst.Add
72 (rule 1 (lower (HighLevelInst.Add
75 (inst_result (HighLevelInst.Add
78 (LowLevelInst.Add
84 (rule (lower (HighLevelInst.Add a (inst_result (HighLevelInst.Const c))))
85 (LowLevelInst.Add
[all …]
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| H A D | let.isle | 1 (type A (enum (Add (x u32) (y u32)) (Sub (x u32) (y u32))))
7 (decl Add (u32 u32) u32)
8 (extern constructor Add add)
13 (Lower (A.Add x y))
14 (let ((z u32 (Add x y)))
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| H A D | test3.isle | 24 (Add (a Reg) (b Reg))
57 (MachInst.Add (UseInput ra) (UseInput rb)))
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| /wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/ |
| H A D | broken_fits_in_32_band.isle | 12 (Add #x00) ;; 0
32 (Add)
43 ;; Add, setting flags
57 ;; Add with carry
59 ;; Add with carrysettings flags
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| H A D | broken_fits_in_32_bor.isle | 12 (Add #x00) ;; 0
32 (Add)
43 ;; Add, setting flags
57 ;; Add with carry
59 ;; Add with carrysettings flags
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| /wasmtime-44.0.1/cranelift/codegen/src/ir/ |
| H A D | atomic_rmw_op.rs | 12 Add, enumerator
39 AtomicRmwOp::Add, in all()
57 AtomicRmwOp::Add => "add", in fmt()
77 "add" => Ok(AtomicRmwOp::Add), in from_str()
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| /wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/shifts/ |
| H A D | broken_ishl_to_do_shift_64.isle | 11 (Add #x00) ;; 0
31 (Add)
42 ;; Add, setting flags
56 ;; Add with carry
58 ;; Add with carrysettings flags
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| H A D | broken_sshr_to_do_shift_fits_in_32.isle | 11 (Add #x00) ;; 0
31 (Add)
42 ;; Add, setting flags
56 ;; Add with carry
58 ;; Add with carrysettings flags
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| H A D | broken_do_shift_32.isle | 7 (Add #x00) ;; 0
27 (Add)
38 ;; Add, setting flags
52 ;; Add with carry
54 ;; Add with carrysettings flags
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| H A D | broken_ushr_to_do_shift_fits_in_32.isle | 11 (Add #x00) ;; 0
31 (Add)
42 ;; Add, setting flags
56 ;; Add with carry
58 ;; Add with carrysettings flags
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| /wasmtime-44.0.1/cranelift/codegen/src/machinst/ |
| H A D | helpers.rs | 4 use core::ops::{Add, BitAnd, Not, Sub};
16 + Add<N, Output = N> in align_to()
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| /wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/iadd/ |
| H A D | broken_base_case.isle | 11 (Add)
24 (rule (add ty x y) (alu_rrr (ALUOp.Add) ty x y))
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| H A D | broken_shift.isle | 22 (Add #x00) ;; 0
39 (Add)
73 (rule (add_shift ty x y z) (alu_rrr_shift (ALUOp.Add) ty x y z))
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| H A D | broken_shift2.isle | 22 (Add #x00) ;; 0
39 (Add)
73 (rule (add_shift ty x y z) (alu_rrr_shift (ALUOp.Add) ty x y z))
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| H A D | broken_imm12.isle | 15 (Add)
29 (rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
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| H A D | broken_imm12_2.isle | 15 (Add)
30 (rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
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| H A D | broken_add_extend.isle | 11 (Add)
106 (rule (add_extend ty x y) (alu_rr_extend_reg (ALUOp.Add) ty x y))
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| /wasmtime-44.0.1/cranelift/isle/ |
| H A D | README.md | 79 (enum (Add (a Value) (b Value))
89 (enum (Add (mode AddrMode))
217 (rule (lower (HighLevelInst.Add a b))
218 (LowLevelInst.Add
259 let expr3_0 = LowLevelInst::Add {
315 (LowLevelInst.Add
383 let expr3_0 = LowLevelInst::Add {
403 (rule (lower (HighLevelInst.Add
409 (LowLevelInst.Add
416 (LowLevelInst.Add
[all …]
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| /wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/isub/ |
| H A D | imm12neg_new.isle | 15 (Add)
29 (rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
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| /wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/broken/isub/ |
| H A D | broken_imm12neg_not_distinct.isle | 15 (Add)
28 (rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
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| H A D | broken_imm12neg.isle | 15 (Add)
30 (rule (add_imm ty x y) (alu_rr_imm12 (ALUOp.Add) ty x y))
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| H A D | broken_shift.isle | 22 (Add #x00) ;; 0
39 (Add)
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| /wasmtime-44.0.1/crates/wasmtime/src/runtime/vm/ |
| H A D | byte_count.rs | 94 .ok_or(ByteCountOutOfBounds(ByteCountOutOfBoundsKind::Add)) in checked_add()
255 Add, enumerator
269 ByteCountOutOfBoundsKind::Add => f.write_str("byte count overflow during addition"), in fmt()
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| /wasmtime-44.0.1/cranelift/bitset/src/ |
| H A D | scalar.rs | 4 use core::ops::{Add, BitAnd, BitOr, Not, Shl, Shr, Sub};
541 + Add<Output = Self>
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| /wasmtime-44.0.1/cranelift/isle/veri/veri_engine/examples/load/ |
| H A D | load_add_panic.isle | 4 ;; Add with 2 loads spec
|