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/pciutils/maint/
H A Drelease.pm14 my $s = {
41 bless $s;
42 return $s;
164 my ($s) = @_;
165 $s->{"PKG"} = $s->{"PACKAGE"} . "-" . $s->{"VERSION"};
222 my $sf = $s->{"DISTDIR"} . "/" . $s->{"PKG"} . "/$f";
230 my ($s) = @_;
242 my ($s) = @_;
323 $s->Test if $s->{"do_test"};
324 $s->MakePatch if $s->{"do_patch"};
[all …]
/pciutils/lib/
H A Dnames-net.c104 GET16(s->counts[i]); in dns_parse_packet()
124 s->sections[i] = p; in dns_parse_packet()
134 s->sec_ptr = s->sections[i]; in dns_init_section()
135 s->sec_end = s->sections[i+1]; in dns_init_section()
141 byte *p = s->sec_ptr; in dns_parse_rr()
149 GET16(s->rr_type); in dns_parse_rr()
150 GET16(s->rr_class); in dns_parse_rr()
151 GET32(s->rr_ttl); in dns_parse_rr()
152 GET16(s->rr_len); in dns_parse_rr()
153 s->rr_data = p; in dns_parse_rr()
[all …]
H A Ddump.c47 dump_validate(char *s, char *fmt) in dump_validate() argument
51 if (*fmt == '#' ? !isxdigit(*s) : *fmt != *s) in dump_validate()
53 fmt++, s++; in dump_validate()
H A Dnames-parse.c22 #define pci_gets(f, l, s) gzgets(f, l, s) argument
55 #define pci_gets(f, l, s) fgets(l, s, f) argument
H A Dphysmem-windows.c122 #define InitializeObjectAttributes(p, n, a, r, s) \ argument
128 (p)->SecurityDescriptor = (s); \
134 #define RtlInitUnicodeString(d, s) \ argument
136 (d)->Length = wcslen(s) * sizeof(WCHAR); \
138 (d)->Buffer = (PWCHAR)(s); \
H A Dinit.c259 pci_strdup(struct pci_access *a, const char *s) in pci_strdup() argument
261 int len = strlen(s) + 1; in pci_strdup()
263 memcpy(t, s, len); in pci_strdup()
/pciutils/compat/
H A Dgetopt.c175 static int my_strlen(const char *s);
455 char *s = nextchar; in _getopt_internal() local
461 while (*s && *s != '=') in _getopt_internal()
462 s++; in _getopt_internal()
466 if (!my_strncmp(p->name, nextchar, s - nextchar)) { in _getopt_internal()
467 if (s - nextchar == my_strlen(p->name)) { in _getopt_internal()
494 if (*s) { in _getopt_internal()
498 optarg = s + 1; in _getopt_internal()
/pciutils/
H A DChangeLog854 (most notably the resolving of ID's).
1404 or unassigned ROM's as we do in show_bases() for the other BAR's.
1889 * pci.ids: Few new ID's.
1919 * pci.ids: New ID's.
1949 * pci.ids: New ID's.
1958 * pci.ids: New ID's.
1975 * pci.ids: Several new ID's.
2007 New ID's, as usually.
2011 * pci.ids: New ID's. As usually.
2022 * pci.ids: New ID's. Again.
[all …]
/pciutils/tests/
H A Dcap-exp-lnkcap220 LnkCap: Port #1, Speed 8GT/s, Width x4, ASPM not supported
24 LnkSta: Speed 8GT/s (ok), Width x4 (ok)
42 LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- DRS-
43 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
363 LnkSta: Speed 8GT/s (ok), Width x4 (ok)
371 LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- DRS-
372 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
695 LnkSta: Speed 2.5GT/s (ok), Width x4 (ok)
710 LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- DRS-
1021 LnkSta: Speed 2.5GT/s (ok), Width x4 (ok)
[all …]
H A Dbridge-ctl-vga1620 LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L1 <16us
24 LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
38 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
85 LnkCap: Port #3, Speed 8GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <16us
89 LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
103 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
H A Dcap-ide20 LnkCap: Port #0, Speed 32GT/s, Width x16, ASPM not supported
24 LnkSta: Speed 32GT/s, Width x16
35 LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
36 LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis-
67 Capabilities: [3b0 v1] Physical Layer 16.0 GT/s <?>
74 Capabilities: [460 v1] Physical Layer 32.0 GT/s <?>
H A Dcap-phy3219 LnkCap: Port #0, Speed 32GT/s, Width x2, ASPM not supported
23 LnkSta: Speed 16GT/s (downgraded), Width x2
34 LnkCap2: Supported Link Speeds: 2.5-32GT/s, Crosslink- Retimer+ 2Retimers+ DRS-
35 LnkCtl2: Target Link Speed: 32GT/s, EnterCompliance- SpeedDis-
66 Capabilities: [198 v1] Physical Layer 16.0 GT/s
71 Capabilities: [1d4 v1] Physical Layer 32.0 GT/s
H A Dcap-aer-root24 LnkCap: Port #3, Speed 8GT/s, Width x8, ASPM L1, Exit Latency L0s <512ns, L1 <16us
28 LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
36 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
344 LnkCap: Port #8, Speed 8GT/s, Width x8, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited
348 LnkSta: Speed 8GT/s, Width x8, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
352 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
H A Dcap-dev322 LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <8us
26 LnkSta: Speed 8GT/s, Width x4
35 LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- Retimer- 2Retimers- DRS-
36 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
H A Dcap-flitmode22 LnkCap: Port #0, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L1 <8us
26 LnkSta: Speed 8GT/s, Width x4
35 LnkCap2: Supported Link Speeds: 2.5-8GT/s, Crosslink- Retimer- 2Retimers- DRS-
36 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
H A Dcap-vc-and-rcl304 LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us
308 LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
602 LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us
606 LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
900 LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us
904 LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
1198 LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us
1202 LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
1739 LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <512ns, L1 <64us
1743 LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
[all …]
H A Dcap-ptm-119 LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM not supported, Exit Latency L0s <64ns, L1 <1us
23 LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt-
26 LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
H A Dcap-doe19 LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s <64ns
23 LnkSta: Speed 2.5GT/s (ok), Width x1 (ok)
31 LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
H A Dcap-dpc27 LnkCap: Port #1, Speed 8GT/s, Width x4, ASPM L1, Exit Latency L0s <4us, L1 <4us
31 LnkSta: Speed 8GT/s, Width x4, TrErr- Train- SlotClk- DLActive+ BWMgmt+ ABWMgmt-
40 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
H A Dcap-pcie-123 LnkCap: Port #1, Speed 5GT/s, Width x4, ASPM L0s L1, Latency L0 <512ns, L1 <4us
27 LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
39 LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance+ SpeedDis-, Selectable De-emphasis: -6dB
H A Dcap-pcie-228 LnkCap: Port #0, Speed 2.5GT/s, Width x4, ASPM L0s L1, Latency L0 <4us, L1 <64us
32 LnkSta: Speed 2.5GT/s, Width x4, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
35 LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-, Selectable De-emphasis: -6dB
H A Dcap-l1-pm20 LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L1, Exit Latency L0s <4us, L1 <32us
24 LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
27 LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
H A Dcap-aer-log20 LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us
24 LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
38 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
H A Dcap-aer-hdr20 LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us
24 LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
38 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
H A Dcap-aer-ecrc-label20 LnkCap: Port #1, Speed 8GT/s, Width x1, ASPM L1, Exit Latency L0s <1us, L1 <16us
24 LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
38 LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-

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