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Searched refs:lane (Results 1 – 6 of 6) sorted by relevance

/pciutils/lmr/
H A Dmargin_results.c48 struct margin_res_lane *lane; in margin_results_print_brief() local
170 lane = &(res->lanes[j]); in margin_results_print_brief()
196 printf("Rx(%X) Lane %2d: %s\t (W %4.1f%% UI - %5.2fps", 10 + res->recvn - 1, lane->lane, in margin_results_print_brief()
204 right_ps, lane->steps[TIM_RIGHT], sts_strings[lane->statuses[TIM_RIGHT]]); in margin_results_print_brief()
213 lane->steps[VOLT_UP], sts_strings[lane->statuses[VOLT_UP]], down_volt, in margin_results_print_brief()
214 lane->steps[VOLT_DOWN], sts_strings[lane->statuses[VOLT_DOWN]]); in margin_results_print_brief()
237 struct margin_res_lane *lane; in margin_results_save_csv() local
307 lane = &(res->lanes[j]); in margin_results_save_csv()
333 fprintf(csv, "%d,%f,", lane->lane, ew_min); in margin_results_save_csv()
353 lane->steps[TIM_LEFT], sts_strings[lane->statuses[TIM_LEFT]]); in margin_results_save_csv()
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H A Dmargin.c60 #define LMR_LANE_CTRL(lmr_cap_addr, lane) ((lmr_cap_addr) + 8 + 4 * (lane)) argument
61 #define LMR_LANE_STATUS(lmr_cap_addr, lane) ((lmr_cap_addr) + 10 + 4 * (lane)) argument
127 margin_set_cmd(struct margin_dev *dev, u8 lane, margin_cmd cmd) in margin_set_cmd() argument
142 && margin_set_cmd(dev, lane, NO_COMMAND); in margin_report_cmd()
168 u8 lane = lane_reversal ? dev->max_width - 1 : 0; in read_params_internal() local
169 margin_set_cmd(dev, lane, NO_COMMAND); in read_params_internal()
241 margin_set_cmd(arg.recv->dev, arg.results[i].lane, NO_COMMAND); in margin_test_lanes()
242 margin_set_cmd(arg.recv->dev, arg.results[i].lane, in margin_test_lanes()
244 margin_set_cmd(arg.recv->dev, arg.results[i].lane, NO_COMMAND); in margin_test_lanes()
368 results->lanes[i].lane in margin_test_receiver()
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H A Dlmr.h71 u8 lane; member
/pciutils/
H A Dls-ecaps.c85 u8 lane; in cap_sec() local
103 for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1) in cap_sec()
105 printf(" %u", lane); in cap_sec()
H A Dpci.ids1219 # Lower lane count PEX89000 switch
1221 # Lower lane count PEX89000 switch
1224 # Lower lane count PEX89000 switch
1226 # Lower lane count PEX89000 switch
1228 # Lower lane count PEX89000 switch
1230 # Lower lane count PEX89000 switch
9417 8505 PEX 8505 5-lane, 5-port PCI Express Switch
9418 8508 PEX 8508 8-lane, 5-port PCI Express Switch
9419 8509 PEX 8509 8-lane, 8-port PCI Express Switch
15089 8018 PES12N3A 12-lane 3-Port PCI Express Switch
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H A DChangeLog86 * Added a pcilmr utility for PCIe lane margining. Thanks to Nikita