Fix formatting of 64-bit integers

PCI_U64_FMT_X is needed.

Tables of strings should have both pointers and the actual strings const

Remove trailing whitespace

Flit Mode and Device 3 Capability

Add CXL DVSEC GPF time_scale 10s support

Ref CXL Spec chapter 8.1.6 and 8.1.7, Add time_scale 10s support.

When time_scale is 7h

Old code shows:
GPF Phase 1 Timeout: 20<?>

New code shows
GPF Ph

Add CXL DVSEC GPF time_scale 10s support

Ref CXL Spec chapter 8.1.6 and 8.1.7, Add time_scale 10s support.

When time_scale is 7h

Old code shows:
GPF Phase 1 Timeout: 20<?>

New code shows
GPF Phase 1 Timeout: 20s

The changes do not affect Reserved time scale encoding shows <?>.

Signed-off-by: yeeli <[email protected]>

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lspci: Decode Physical Layer 64 GT/s extended capability register

lspci: Decode Physical Layer 16 GT/s and 32 GT/s extended capability registers

ls-ecaps: extend decode support for more fields for AER CE and UE status

Extend decode support for more fields for AER CE and UE status prior to
PCIe r6.0.

Signed-off-by: Shuai Xue <xueshuai@linux.

ls-ecaps: extend decode support for more fields for AER CE and UE status

Extend decode support for more fields for AER CE and UE status prior to
PCIe r6.0.

Signed-off-by: Shuai Xue <[email protected]>

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ls-ecaps: Correct the link state reporting

PCIe r6.0, sec 7.9.26.4.2 "Link IDE Stream Status Register defines"
the link state as:

0000b Insecure
0010b Secure

The same definition applies to selecti

ls-ecaps: Correct the link state reporting

PCIe r6.0, sec 7.9.26.4.2 "Link IDE Stream Status Register defines"
the link state as:

0000b Insecure
0010b Secure

The same definition applies to selective streams as well.
The existing code wrongly assumes "secure" is 0001b, fix that for both
link and selective streams.

While at this, add missing "Selective IDE for Configuration Requests Enable".
Also fix the base and limit parsing for the memory and RID ranges.

Fixes: 42fc4263ec0e ("ls-ecaps: Add decode support for IDE Extended Capability")
Signed-off-by: Alexey Kardashevskiy <[email protected]>

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ls-ecaps: Add decode support for IDE Extended Capability

IDE (Integrity & Data Encryption) Extended Capability defined in [1]
implements control of the PCI link encryption. The verbose level > 2 pri

ls-ecaps: Add decode support for IDE Extended Capability

IDE (Integrity & Data Encryption) Extended Capability defined in [1]
implements control of the PCI link encryption. The verbose level > 2 prints
offsets of the fields to make running setpci easier.

The example output is:

Capabilities: [830 v1] Integrity & Data Encryption
IDECap: Lnk=0 Sel=1 FlowThru- PartHdr- Aggr- PCPC- IDE_KM+ Alg='AES-GCM-256-96b' TCs=8 TeeLim+
IDECtl: FTEn-
SelectiveIDE#0 Cap: RID#=1
SelectiveIDE#0 Ctl: En- NPR- PR- CPL- PCRC- HdrEnc=no Alg='AES-GCM-256-96b' TC0 ID0
SelectiveIDE#0 Sta: insecure RecvChkFail-
SelectiveIDE#0 RID: Valid- Base=0 Limit=0 SegBase=0
SelectiveIDE#0 RID#0: Valid- Base=0 Limit=0

[1] PCIe r6.0.1, sections 6.33, 7.9.26

Signed-off-by: Alexey Kardashevskiy <[email protected]>

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lspci: Add Lane Margining support to the lspci

Gather all the info available without writing to the config space.
Without any commands margining capability exposes only 3 status bits to
read through

lspci: Add Lane Margining support to the lspci

Gather all the info available without writing to the config space.
Without any commands margining capability exposes only 3 status bits to
read through Margining Port Capabilities and Margining Port Status registers.
It makes sense to show them anyway. For example, Margining Ready bit
indicates whether the device is actually ready for the margining process.

Reviewed-by: Sergei Miroshnichenko <[email protected]>
Signed-off-by: Nikita Proshkin <[email protected]>

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Constants for CXL capability should not change

When CXL capability decoding was upgraded to revision 2 by commit
c0ccce1b4cd5b42b17f2e8f7bae4031c311677ff, the value of PCI_CXL_DEV_LEN
in lib/header.

Constants for CXL capability should not change

When CXL capability decoding was upgraded to revision 2 by commit
c0ccce1b4cd5b42b17f2e8f7bae4031c311677ff, the value of PCI_CXL_DEV_LEN
in lib/header.h has changed.

This is probably not a good idea - programs using libpci can depend
on the exact value of this constant.

Let us revert PCI_CXL_DEV_LEN to the original value for revision 1
and add PCI_CXL_DEV_LEN_REV2 for the next revision.

Also, fixed a bug in the decoder which caused it to read past the
end of the buffer for a capability which is declared as revision 2,
but too short.

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CXL: Fix indentation

Subject: lspci: Display PASID required attribute in Page Status Register.

Display the PASID required attribute in the Page Request Status Register.
When set, the function expects a PASID on Page Gro

Subject: lspci: Display PASID required attribute in Page Status Register.

Display the PASID required attribute in the Page Request Status Register.
When set, the function expects a PASID on Page Group Response (PRG)
messages when the corresponding page request had a PASID.

Signed-off-by: Ashok Raj <[email protected]>

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lspci: Remove spurious colon (':') from PCIe PTM decoding

Remove spurious colon from PTM decoding to match other enabled/disabled
decoding.

Signed-off-by: Bjorn Helgaas <[email protected]>

lspci: Print PCIe Interrupt Message Numbers consistently

Several Capabilities include MSI/MSI-X Interrupt Message Numbers, which
were decoded in various ways:

- MSI %02x

lspci: Print PCIe Interrupt Message Numbers consistently

Several Capabilities include MSI/MSI-X Interrupt Message Numbers, which
were decoded in various ways:

- MSI %02x PCIe Capability
- IntMsg %d AER Capability
- INT Msg #%d DPC Capability
- Interrupt Message Number %03x SR-IOV Capability
- Interrupt Message Number %03x DOE Capability

Print them all using the same format:

+ IntMsgNum %d

This better matches the "Interrupt Message Number" terminology used in the
spec, e.g., PCIe r6.0, sec 7.5.3.2.

Signed-off-by: Bjorn Helgaas <[email protected]>
Cc: Jonathan Cameron <[email protected]>

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Add support for 32.0 GT/s header

Update license comments and added SPDX license identifiers

Previously, the only information about the specific version of GPL
was present in the README and individual source files mentioned only
GPL

Update license comments and added SPDX license identifiers

Previously, the only information about the specific version of GPL
was present in the README and individual source files mentioned only
GPL alone.

Let us update all copyright comments to explicitly say "GPL v2+"
and also include the machine readable SPDX license identifier.

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CXL3.0: Add DVSEC CXLCtrl3 and missing CXLCtl2

8.1.3 PCIe DVSEC for CXL Devices

CXL: Fix Flex Bus DVSEC cap

lspci: Add support for Non-CXL Function Map DVSEC

Add Non-CXL Function Map DVSEC Registers 0-7 decoding according to
DVSEC Revision ID 0.

Signed-off-by: Jaxon Haws <[email protected]>

lspci: Add support for CXL MLD DVSEC

Add MLD DVSEC decoding for CXL device accoring to DVSEC revision ID 0.
Decode Number of Logical Devices Supported.

Signed-off-by: Jaxon Haws <[email protected]>

lspci: Add support for CXL GPF Port DVSEC

Add Global Persistent Flush DVSEC decoding for CXL port according to
DVSEC Revision ID 0.
Decode GPF Phase 1 Control and GPF Phase 2 Control.

Signed-off-by

lspci: Add support for CXL GPF Port DVSEC

Add Global Persistent Flush DVSEC decoding for CXL port according to
DVSEC Revision ID 0.
Decode GPF Phase 1 Control and GPF Phase 2 Control.

Signed-off-by: Jaxon Haws <[email protected]>

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lspci: Add support for CXL Flex Bus DVSEC

Add DVSEC Flex Bus Port for CXL devices according to DVSEC Revision ID 1,
capability decoding, control decoding, and status decoding.

Signed-off-by: Jaxon

lspci: Add support for CXL Flex Bus DVSEC

Add DVSEC Flex Bus Port for CXL devices according to DVSEC Revision ID 1,
capability decoding, control decoding, and status decoding.

Signed-off-by: Jaxon Haws <[email protected]>

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lspci: Add support for CXL GPF Device DVSEC

Add Global Persistent Flush DVSEC decoding for CXL device according to
DVSEC Revision ID 0.
Decode GPF Phase 2 Duration and GPF Phase 2 Power.

Signed-off

lspci: Add support for CXL GPF Device DVSEC

Add Global Persistent Flush DVSEC decoding for CXL device according to
DVSEC Revision ID 0.
Decode GPF Phase 2 Duration and GPF Phase 2 Power.

Signed-off-by: Jaxon Haws <[email protected]>

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