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/llvm-project-15.0.7/llvm/test/Analysis/BasicAA/
H A Dq.bad.ll89 %zext.zext.sext.255 = zext i32 %zext.sext.255 to i64
90 %zext.sext.zext.255 = zext i32 %sext.zext.255 to i64
106 %zext.zext.sext.num = zext i32 %zext.sext.num to i64
107 %zext.sext.zext.num = zext i32 %sext.zext.num to i64
138 %zext.4 = zext i3 %zext.plus.4 to i32
139 %zext.7 = zext i3 %zext.plus.7 to i32
157 %zext.4 = zext i8 %zext.plus.4 to i32
158 %zext.7 = zext i8 %zext.plus.7 to i32
176 %zext.4 = zext i3 %zext.plus.4 to i32
177 %zext.7 = zext i3 %zext.plus.7 to i32
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/
H A Dzext-divrem.ll6 %zext = zext i32 %div to i64
7 ; CHECK: %zext
9 ret i64 %zext
15 %zext = zext i32 %rem to i64
16 ; CHECK: %zext
17 ; CHECK-NEXT: --> ((zext i32 %a to i64) + (-1 * (zext i32 %b to i64) * ((zext i32 %a to i64) /u (z…
18 ret i64 %zext
26 %zext = zext i32 %sub to i64
27 ; CHECK: %zext
28 ; CHECK-NEXT: --> ((zext i32 %a to i64) + (-1 * (zext i32 %b to i64) * ((zext i32 %a to i64) /u (z…
[all …]
H A Dumin-umax-folds.ll7 ; CHECK-NEXT: %len.zext = zext i32 %len to i64
25 %len.zext = zext i32 %len to i64
42 ; CHECK-NEXT: %len.zext = zext i32 %len to i64
60 %len.zext = zext i32 %len to i64
95 %len.zext = zext i32 %len to i64
130 %len.zext = zext i32 %len to i64
165 %len.zext = zext i32 %len to i64
200 %len.zext = zext i32 %len to i64
235 %len.zext = zext i32 %len to i64
270 %len.zext = zext i32 %len to i64
[all …]
H A Dno-wrap-add-exprs.ll126 %t0.zext = zext i8 %t0 to i16
127 %t1.zext = zext i8 %t1 to i16
131 %q0.zext = zext i8 %q0 to i16
132 %q1.zext = zext i8 %q1 to i16
237 %t1.zext = zext i8 %t1 to i16
241 %q1.zext = zext i8 %q1 to i16
245 %p1.zext = zext i8 %p1 to i16
249 %r1.zext = zext i8 %r1 to i16
256 %s3.zext = zext i8 %s3 to i16
261 %int.zext = zext i32 %int5 to i64
[all …]
H A Dmax-backedge-taken-count-guard-info-rewrite-expressions.ll10 ; CHECK-NEXT: %ext = zext i32 %n to i64
26 %ext = zext i32 %n to i64
51 ; CHECK-NEXT: %ext = zext i32 %umin to i64
70 %ext = zext i32 %umin to i64
124 %ext = zext i32 %and.sub.1 to i64
172 %ext = zext i32 %and.sub.1 to i64
192 ; CHECK-NEXT: %ext = zext i32 %n to i64
208 %ext = zext i32 %n to i64
236 ; CHECK-NEXT: %ext = zext i32 %n to i64
252 %ext = zext i32 %n to i64
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dcmp_ext.ll12 %zext = zext i32 %x to i64
22 %zext = zext i32 %x to i64
35 %zext = zext i32 %x to i64
45 %zext = zext i32 %x to i64
55 %zext = zext i32 %x to i64
68 %zext = zext i32 %x to i64
78 %zext = zext i32 %x to i64
91 %zext = zext i32 %x to i64
101 %zext = zext i32 %x to i64
114 %zext = zext i32 %x to i64
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Doverflow-mul.ll14 ; return mul(zext x, zext y) > MAX
20 ; CHECK-NOT: zext i32
29 ; return mul(zext x, zext y) >= MAX+1
35 ; CHECK-NOT: zext i32
44 ; mul(zext x, zext y) > MAX
63 ; return mul(zext x, zext y) > MAX
77 ; return mul(zext x, zext y) <= MAX
93 ; return mul(zext x, zext y) < MAX+1
127 ; mul(zext x, zext y) != zext trunc mul
143 ; mul(zext x, zext y) == zext trunc mul
[all …]
H A Dudivrem-change-width.ll11 %za = zext i8 %a to i32
12 %zb = zext i8 %b to i32
35 %za = zext i8 %a to i32
36 %zb = zext i8 %b to i32
60 %za = zext i8 %a to i32
61 %zb = zext i8 %b to i32
87 %za = zext i8 %a to i32
88 %zb = zext i8 %b to i32
101 %za = zext i9 %a to i32
102 %zb = zext i9 %b to i32
[all …]
H A Dzext.ll9 %c1 = zext i16 %A to i32
21 %zext = zext <2 x i1> %xor to <2 x i64>
22 ret <2 x i64> %zext
32 %zext = zext <2 x i32> %and to <2 x i64>
33 ret <2 x i64> %zext
45 %zext = zext <2 x i32> %xor to <2 x i64>
46 ret <2 x i64> %zext
73 ; Assert that zexts in and(zext(icmp), zext(icmp)) can be folded.
84 %2 = zext i1 %1 to i8
91 ; Assert that zexts in or(zext(icmp), zext(icmp)) can be folded.
[all …]
H A Dicmp-and-shift.ll15 %conv = zext i1 %cmp to i32
41 %conv = zext i1 %cmp to i32
67 %conv = zext i1 %cmp to i32
93 %conv = zext i1 %cmp to i32
121 %conv = zext i1 %cmp to i32
134 %conv = zext i1 %cmp to i32
145 %conv = zext i1 %cmp to i32
159 %conv = zext i1 %cmp to i32
185 %conv = zext i1 %cmp to i32
211 %conv = zext i1 %cmp to i32
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopUnrollAndJam/
H A Dunroll-and-jam-many-instr.ll37 %lor.ext = zext i1 %tobool21 to i32
314 %conv = zext i8 %3 to i32
316 %conv7 = zext i1 %cmp to i32
319 %conv.1 = zext i8 %4 to i32
324 %conv.2 = zext i8 %5 to i32
329 %conv.3 = zext i8 %6 to i32
334 %conv.4 = zext i8 %7 to i32
339 %conv.5 = zext i8 %8 to i32
344 %conv.6 = zext i8 %9 to i32
349 %conv.7 = zext i8 %10 to i32
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/
H A Dtrunc_shl.ll10 %zext = zext i8 %x to i32
11 %shl = shl i32 %zext, 1
22 %zext = zext i8 %x to i32
23 %shl = shl i32 %zext, 15
37 %zext = zext i8 %x to i32
53 %zext.x = zext i8 %x to i32
54 %zext.y = zext i8 %y to i32
55 %shl = shl i32 %zext.x, %zext.y
68 %zext.x = zext i8 %x to i32
69 %zext.y = zext i8 %y to i32
[all …]
H A Dtrunc_udivrem.ll10 %zext = zext i8 %x to i32
11 %div = udiv i32 %zext, 42
21 %zextx = zext i16 %x to i32
22 %zexty = zext i16 %y to i32
36 %zext = zext i8 %x to i32
37 %div = udiv i32 %zext, 70000
87 %zextx = zext i16 %x to i32
88 %zexty = zext i16 %y to i32
101 %zext = zext i8 %x to i32
102 %div = urem i32 %zext, 42
[all …]
H A Dtrunc_ashr.ll14 %zext = zext i16 %x to i32
15 %ashr = ashr i32 %zext, 15
40 %zext = zext i16 %x to i32
41 %ashr = ashr i32 %zext, 16
58 %z = zext i8 %x to i32
59 %za = zext i8 %amt to i32
77 %z = zext i8 %x to i32
98 %zext = zext i32 %x to i64
215 %zext = zext i16 %x to i32
232 %zext = zext i16 %x to i32
[all …]
H A Dtrunc_lshr.ll9 %zext = zext i16 %x to i32
10 %lshr = lshr i32 %zext, 15
24 %zext = zext i16 %x to i32
25 %lshr = lshr i32 %zext, 16
42 %z = zext i8 %x to i32
43 %za = zext i8 %amt to i32
61 %z = zext i8 %x to i32
62 %za = zext i8 %amt to i32
82 %zext = zext i32 %x to i64
198 %zext = zext i16 %x to i32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpreserve-hi16.ll97 %zext = zext i16 %res to i32
107 %zext = zext i16 %res to i32
117 %zext = zext i16 %res to i32
127 %zext = zext i16 %res to i32
137 %zext = zext i16 %res to i32
147 %zext = zext i16 %res to i32
158 %zext = zext i16 %res to i32
169 %zext = zext i16 %res to i32
180 %zext = zext i16 %res to i32
191 %zext = zext i16 %res to i32
[all …]
H A Dglobal-saddr-store.ll24 %zext.offset = zext i32 %voffset to i64
47 %zext.offset = zext i32 %voffset to i64
71 %zext.offset = zext i32 %voffset to i64
118 %zext.offset = zext i32 %voffset to i64
158 %zext.offset = zext i32 %voffset to i64
180 %zext.offset = zext i32 %voffset to i64
198 %zext.offset = zext i32 %voffset to i64
217 %zext.offset = zext i32 %voffset to i64
235 %zext.offset = zext i32 %voffset to i64
254 %zext.offset = zext i32 %voffset to i64
[all …]
H A Dglobal-saddr-load.ll28 %zext = zext i8 %load to i32
57 %zext = zext i8 %load to i32
79 %zext = zext i8 %load to i32
101 %zext = zext i8 %load to i32
131 %zext = zext i8 %load to i32
165 %zext = zext i8 %load to i32
199 %zext = zext i8 %load to i32
228 %zext = zext i8 %load to i32
257 %zext = zext i8 %load to i32
286 %zext = zext i8 %load to i32
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dneon-abd.ll200 %sub = sub <8 x i16> %a.zext, %b.zext
213 %sub = sub <16 x i16> %a.zext, %b.zext
226 %sub = sub <4 x i32> %a.zext, %b.zext
241 %sub = sub <4 x i16> %a.zext, %b.zext
253 %sub = sub <8 x i32> %a.zext, %b.zext
266 %sub = sub <8 x i16> %a.zext, %b.zext
278 %sub = sub <2 x i64> %a.zext, %b.zext
294 %sub = sub <2 x i32> %a.zext, %b.zext
306 %sub = sub <4 x i64> %a.zext, %b.zext
319 %sub = sub <4 x i32> %a.zext, %b.zext
[all …]
H A Dsve-masked-gather-32b-unsigned-unscaled.ll14 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
17 %vals.zext = zext <vscale x 2 x i8> %vals to <vscale x 2 x i64>
26 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
30 %vals.zext = zext <vscale x 2 x i16> %vals to <vscale x 2 x i64>
39 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
43 %vals.zext = zext <vscale x 2 x i32> %vals to <vscale x 2 x i64>
52 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
64 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
76 %offsets.zext = zext <vscale x 2 x i32> %offsets to <vscale x 2 x i64>
157 %vals.zext = zext <vscale x 4 x i8> %vals to <vscale x 4 x i32>
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dzext.ll39 %x0 = zext i8 %i0 to i64
40 %x1 = zext i8 %i1 to i64
72 %x0 = zext i8 %i0 to i32
73 %x1 = zext i8 %i1 to i32
74 %x2 = zext i8 %i2 to i32
75 %x3 = zext i8 %i3 to i32
109 %x0 = zext i8 %i0 to i64
110 %x1 = zext i8 %i1 to i64
111 %x2 = zext i8 %i2 to i64
112 %x3 = zext i8 %i3 to i64
[all …]
H A Dzext-inseltpoison.ll39 %x0 = zext i8 %i0 to i64
40 %x1 = zext i8 %i1 to i64
72 %x0 = zext i8 %i0 to i32
73 %x1 = zext i8 %i1 to i32
74 %x2 = zext i8 %i2 to i32
75 %x3 = zext i8 %i3 to i32
109 %x0 = zext i8 %i0 to i64
110 %x1 = zext i8 %i1 to i64
111 %x2 = zext i8 %i2 to i64
112 %x3 = zext i8 %i3 to i64
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dint-conv-11.ll77 %ext0 = zext i8 %trunc0 to i32
78 %ext1 = zext i8 %trunc1 to i32
79 %ext2 = zext i8 %trunc2 to i32
80 %ext3 = zext i8 %trunc3 to i32
81 %ext4 = zext i8 %trunc4 to i32
82 %ext5 = zext i8 %trunc5 to i32
83 %ext6 = zext i8 %trunc6 to i32
84 %ext7 = zext i8 %trunc7 to i32
85 %ext8 = zext i8 %trunc8 to i32
86 %ext9 = zext i8 %trunc9 to i32
[all …]
/llvm-project-15.0.7/llvm/test/Bitcode/
H A Dbitcode-parseconstant-delay-select.ll11 …zext (i1 icmp eq (i32* getelementptr inbounds ([3 x i32], [3 x i32]* @c, i64 0, i64 2), i32* @a) t…
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A DAtomics-64.ll215 %1 = zext i8 %0 to i32
221 %6 = zext i8 %5 to i32
227 %11 = zext i8 %10 to i32
233 %16 = zext i8 %15 to i32
239 %21 = zext i8 %20 to i32
244 %25 = zext i8 %24 to i32
249 %29 = zext i8 %28 to i64
254 %33 = zext i8 %32 to i64
557 %1 = zext i8 %0 to i32
559 %3 = zext i8 %2 to i32
[all …]

12345678910>>...146