Home
last modified time | relevance | path

Searched refs:writeback (Results 1 – 25 of 32) sorted by relevance

12

/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-diags.s155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
185 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
224 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
227 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
230 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
233 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
236 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
239 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
242 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb-diagnostics.s87 @ Invalid writeback and register lists for LDM
103 @ CHECK-ERRORS: error: writeback operator '!' expected
106 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
109 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
112 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
137 @ Invalid writeback and register lists for PUSH/POP
148 @ Invalid writeback and register lists for STM
165 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
168 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
H A Ddiagnostics.s542 @ CHECK-ERRORS: error: writeback register not allowed in register list
543 @ CHECK-ERRORS: error: writeback register not allowed in register list
544 @ CHECK-ERRORS: error: writeback register not allowed in register list
545 @ CHECK-ERRORS: error: writeback register not allowed in register list
566 @ CHECK-ERRORS: error: system STM cannot have writeback register
567 @ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list
H A Darm-load-store-multiple-deprecated.s153 @ CHECK-V7: error: writeback register not allowed in register list
155 @ CHECK-V7: error: writeback register not allowed in register list
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcortex-a57-misched-stm-wrback.ll3 ; N=3 STMIA_UPD should have latency 2cyc and writeback latency 1cyc
/llvm-project-15.0.7/clang/lib/CodeGen/
H A DCGCall.h305 Writeback writeback = {srcLV, temporary, toUse}; in addWriteback() local
306 Writebacks.push_back(writeback); in addWriteback()
H A DCGCall.cpp3826 const CallArgList::Writeback &writeback) { in emitWriteback() argument
3827 const LValue &srcLV = writeback.Source; in emitWriteback()
3849 llvm::Value *value = CGF.Builder.CreateLoad(writeback.Temporary); in emitWriteback()
3862 if (writeback.ToUse) { in emitWriteback()
3870 CGF.EmitARCIntrinsicUse(writeback.ToUse); in emitWriteback()
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-unpredictable.txt84 # Also unpredictable if writeback clashes with either transfer register
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td66 // consumes the pipe for one cycle at issue and another cycle at writeback.
95 // but only consume the pipe for one cycle at issue and a cycle at writeback.
208 // The ID pipe is consumed for 2 cycles: issue and writeback.
215 // The ID pipe is consumed for 2 cycles: issue and writeback.
633 // Only the first WriteVLD and WriteAdr for writeback matches def operands.
774 // Only the WriteAdr for writeback matches a def operands.
/llvm-project-15.0.7/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2098 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction() local
2100 if (P && writeback) in DecodeAddrMode2IdxInstruction()
2102 else if (!P && writeback) in DecodeAddrMode2IdxInstruction()
2105 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
2219 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction() local
2272 if (!type && writeback && Rn == 15) in DecodeAddrMode3Instruction()
2314 if (writeback) { // Writeback in DecodeAddrMode3Instruction()
2352 if (writeback) { in DecodeAddrMode3Instruction()
5886 bool writeback = (W == 1) | (P == 0); in DecodeT2LDRDPreInstruction() local
5890 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeT2LDRDPreInstruction()
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dldst-opt-mte.mir274 # This case can not be merged because the source register is always read before writeback.
H A Dldst-opt-mte-with-dbg.mir361 # This case can not be merged because the source register is always read before writeback.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleM7.td30 // EX3: slow load data integer writeback FP operation
31 // EX4: store data FP writeback
H A DARMScheduleA9.td447 // register file writeback!).
2336 // A9WriteAdr consumes AGU regardless address writeback. But it's
2346 // Store either has no def operands, or the one def for address writeback.
2364 // Load multiple with address writeback has an extra def operand in
2368 // resources are identical, For stores only the address writeback
2383 // Note: Unlike VLDM, VLD1 expects the writeback operand after the
2404 // address writeback.
H A DARMScheduleA57.td592 // TODO: no writeback latency defined in documentation (implemented as 1 cyc)
626 // Store, immed pre-indexed (1cyc "S, I0/I1", 1cyc writeback)
688 // TODO: no writeback latency defined in documentation
1263 // 1-2 reg: 5cyc L, +I for writeback, 1 cyc wb latency
1268 // 3-4 reg: 6cyc L, +I for writeback, 1 cyc wb latency
H A DARMInstrNEON.td626 // ...with address register writeback:
826 // ...with address register writeback:
899 // ...with address register writeback:
959 // ...with address register writeback:
1115 // ...with address register writeback:
1178 // ...with address register writeback:
1249 // ...with address register writeback:
1327 // ...with address register writeback:
1419 // ...with address register writeback:
1501 // ...with address register writeback:
[all …]
H A DARMInstrMVE.td5986 let Inst{21} = writeback;
6002 // A parameter class used to encapsulate all the ways the writeback
6003 // variants of VLD20 and friends differ from the non-writeback ones.
6006 bit writeback = b;
6037 : MVE_vldst24_base<wb.writeback, n.bit0, pat, size, 1,
6046 : MVE_vldst24_base<wb.writeback, n.bit0, pat, size, 0,
6054 // vector lane; writeback or no writeback.
6243 // generate three writeback modes (none, preindex, postindex).
6473 // writeback, in which the address vector is updated to hold the
6491 // Multiclass that generates the non-writeback and writeback variants.
[all …]
H A DARMInstrVFP.td235 let Inst{21} = 0; // No writeback
263 let Inst{21} = 0; // No writeback
370 let Inst{21} = 0; // No writeback
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-thumbv7.txt360 # 32-bit Thumb STM instructions cannot have a writeback register which appears
/llvm-project-15.0.7/clang/docs/
H A DAutomaticReferenceCounting.rst957 * the conversion is a well-formed :ref:`pass-by-writeback
1040 Passing to an out parameter by writeback
1045 candidate for :arc-term:`pass-by-writeback`` if:
1051 a pass-by-writeback is always worse than an implicit conversion sequence not
1052 requiring a pass-by-writeback.
1054 The pass-by-writeback is ill-formed if the argument expression does not have a
1071 below, where their store to the writeback temporary is not immediately seen
1074 A pass-by-writeback is evaluated as follows:
1078 and no further work is required for the pass-by-writeback.
1417 caution in the following rules about writeback.
/llvm-project-15.0.7/llvm/docs/
H A DAMDGPUUsage.rst6451 Subsequent access from the GPU will automatically invalidate or writeback
6454 invalidation or writeback is required for coherence.
6456 different agents a ``buffer_wbl2`` is required. It will writeback dirty L2
7367 - Performs L2 writeback to
7411 writeback have
7551 writeback have
8844 Subsequent access from the GPU will automatically invalidate or writeback
8848 agent is configured to have a single L2, or will writeback dirty L2 cache
8851 ``buffer_wbl2 sc1`` is required. It will writeback dirty L2 cache lines.
9783 writeback have
[all …]
/llvm-project-15.0.7/clang/test/CodeGenObjCXX/
H A Darc.mm298 // a non-dependent message send that requires writeback.
/llvm-project-15.0.7/llvm/test/CodeGen/WebAssembly/
H A Duserstack.ll168 ; Decrement SP in the prolog by the static amount and writeback to memory.
/llvm-project-15.0.7/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1468 unsigned writeback = fieldFromInstruction(insn, 11, 1); in DecodeAuthLoadInstruction() local
1487 if (writeback && Rt == Rn && Rn != 31) { in DecodeAuthLoadInstruction()
/llvm-project-15.0.7/clang/include/clang/Basic/
H A Darm_mve.td303 // Straightforward case with neither writeback nor predication
308 // Predicated form without writeback
322 // Both writeback and predicated

12