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/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dfirst-order-recurrence.ll55 ; widened, the second is a cast that will be widened and needs to sink after the
57 ; instead of widened. Although the cast and the first instruction will both be
58 ; widened, and are originally adjacent to each other, make sure the replicated
88 store i32 7, i32* %arraycidx ; 1st instruction, to be widened.
90 %1 = load i16, i16* %cur.index ; 3rd, first-order-recurring load not widened.
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Drelax-per-target-feature.ll17 ; Function has thumb2 target-feature, tail call is allowed and must be widened.
27 ; generated as it cannot be widened.
H A Dwiden-vmovs.ll8 ; The vmovs is first widened to a vmovd, and then converted to a vorr because of the v2f32 vadd.f32.
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dvect-phiscev-sext-trunc.ll9 ; that these casts, do not get vectorized/scalarized/widened.
40 ; In the case of widened induction, this means that the induction phi
87 ; the induction is not vectorized but rather only the step is widened.
108 ; In the case of widened induction, this means that the induction phi
H A Dskip-iterations.ll8 ; safely speculating that the widened load of A[i] should not fault if the
107 ; we handle the speculation safety of the widened load).
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dlegalize-load-memory-metadata.mir57 # Result register type already matches the widened memory type.
94 # Result register type already matches the widened memory type.
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dsve-widen-scalable-vectortype.ll4 ; properly widened to part vectors.
H A Dbitcast-promote-widen.ll4 ; Test cases of bitcasts where one type needs to be widened and one needs to be promoted.
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dftrunc-legalize.ll4 ; This would assert because the widened vector op is
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/Hexagon/
H A Dinvalidate-cm-after-invalidating-interleavegroups.ll13 ; Also make sure the loads are not widened.
60 ; Make sure the loads are not widened.
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dzve32-types.ll9 ; NOTE: The load and store are widened by using VP_LOAD/STORE. The add/fadd are
10 ; widened by using the next larger LMUL and operating on the whole vector. This
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.td27 // Match if this specific argument was widened from a short vector type.
57 // Sub-128 vectors are returned in the same way, but they're widened
121 // are passed in the same way, but they're widened to one of these types
253 // are passed in the same way, but they're widened to one of these types
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dpow-libcall.ll4 ; Ensure vectorized FPOWs are not widened/unrolled such that they get lowered
H A Dfrem-libcall.ll4 ; Ensure vectorized FREMs are not widened/unrolled such that they get lowered
/llvm-project-15.0.7/llvm/test/Instrumentation/AddressSanitizer/
H A Dasan-vs-gvn.ll2 ; ASAN conflicts with load widening iff the widened load accesses data out of bounds
/llvm-project-15.0.7/clang-tools-extra/docs/clang-tidy/checks/bugprone/
H A Dimplicit-widening-of-multiplication-result.rst7 widened, and suggests (with fix-it) to either silence the code by making
/llvm-project-15.0.7/clang/test/OpenMP/
H A Dparallel_for_simd_codegen.cpp659 void widened(float *a, float *b, float *c, float *d) { in widened() function
H A Dfor_simd_codegen.cpp714 void widened(float *a, float *b, float *c, float *d) { in widened() function
H A Dsimd_codegen.cpp566 void widened(float *a, float *b, float *c, float *d) { in widened() function
/llvm-project-15.0.7/llvm/docs/Proposals/
H A DVectorizationPlan.rst45 vectorizer. The output IR contains code that has been vectorized or "widened"
145 instructions; e.g., cloned once, replicated multiple times or widened
192 cast may sink past a later instruction and be widened to handle first-order
/llvm-project-15.0.7/llvm/test/DebugInfo/Generic/
H A Dindvar-discriminator.ll3 ; When the induction variable is widened by indvars, check that the debug loc
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/AMDGPU/
H A Dno-widen-to-i64.ll5 ; Induction variables should not be widened for 64-bit integers,
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/X86/
H A Div-widen.ll221 ; check that the induction variable of the inner loop has been widened after indvars.
232 ; check that the induction variable of the inner loop has been widened after indvars.
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Delim-extend.ll110 ; %innercount is currently blocked by lcssa, so is not widened.
111 ; %inneriv can be widened only after proving it has no signed-overflow
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dshufflevec-bitcast-inseltpoison.ll141 ; Negative test - the 2nd mask can't be widened
156 ; Negative test - the 2nd mask can't be widened

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