Home
last modified time | relevance | path

Searched refs:vtype (Results 1 – 22 of 22) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dvmv-copy.mir18 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
35 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
52 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
53 $v28m4 = PseudoVMV_V_I_M4 0, $noreg, 5, implicit $vl, implicit $vtype
69 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
87 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
110 $x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
112 $x15 = PseudoVSETVLI $x17, 73, implicit-def $vl, implicit-def $vtype
114 $x0 = PseudoVSETVLIX0 $x0, 82, implicit-def $vl, implicit-def $vtype
181 $x15 = PseudoVSETIVLI 4, 73, implicit-def $vl, implicit-def $vtype
[all …]
H A Dvsetvli-insert.mir124 … dead $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
163 … dead $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
234 …-NEXT: dead $x0 = PseudoVSETIVLI 0, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
235 …K-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 [[COPY]], 6 /* e64 */, implicit $vtype
269 …-NEXT: dead $x0 = PseudoVSETIVLI 2, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
308 …-NEXT: dead $x0 = PseudoVSETIVLI 2, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
313 …-NEXT: dead $x0 = PseudoVSETIVLI 2, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
355 …NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
362 %3:gprnox0 = PseudoVSETVLI %2, 88, implicit-def dead $vl, implicit-def dead $vtype
422 …-NEXT: dead $x0 = PseudoVSETIVLI 4, 89 /* e64, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
[all …]
H A Dvsetvli-insert-crossbb.mir299 …ECK-NEXT: PseudoVSE64_V_M1 [[PHI]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
378 …-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 [[PHI]], 6 /* e64 */, implicit $vtype
439 …XT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
467 %0:gprnox0 = PseudoVSETVLI %7, 88, implicit-def dead $vl, implicit-def dead $vtype
597 …T: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
665 …T: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
758 …EXT: dead $x0 = PseudoVSETIVLI 4, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
785 …EXT: dead $x0 = PseudoVSETIVLI 1, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
841 ; CHECK-NEXT: %t6:vr = PseudoVMSEQ_VI_M1 %t1, 0, -1, 6 /* e64 */, implicit $vl, implicit $vtype
847 …HECK-NEXT: %mask:vr = PseudoVMANDN_MM_MF8 %t6, %t3, -1, 0 /* e8 */, implicit $vl, implicit $vtype
[all …]
H A Dreg-coalescing.mir16 …rm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %0.sub_vrm2_0, 0, 1, 5 /* e32 */, implicit $vl, implicit $vtype
18 …VSUXSEG2EI32_V_M2_M2 %2, $x10, [[PseudoVLE32_V_M2_]], 1, 5 /* e32 */, implicit $vl, implicit $vtype
22 …b_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %0.sub_vrm2_0:vrn2m2, 0, 1, 5, implicit $vl, implicit $vtype
24 PseudoVSUXSEG2EI32_V_M2_M2 %2:vrn2m2, $x10, %1:vrm2, 1, 5, implicit $vl, implicit $vtype
H A Daliases.mir27 $v25 = VXOR_VI killed $v25, -1, $v0, implicit $vtype, implicit $vl
38 $v1 = VXOR_VI killed $v25, -1, $v0, implicit $vtype, implicit $vl
49 $v25 = VXOR_VI killed $v25, -1, $noreg, implicit $vtype, implicit $vl
60 $v1 = VXOR_VI killed $v25, -1, $noreg, implicit $vtype, implicit $vl
H A Dmask-reg-alloc.mir19 …K-NEXT: dead $x0 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
20 …_VIM_M1 killed renamable $v2, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
22 …_VIM_M1 killed renamable $v3, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
23 …VADD_VV_M1 killed renamable $v8, killed renamable $v9, 1, 3 /* e8 */, implicit $vl, implicit $vtype
H A Dcommuted-op-indices-regression.mir33 …M1 [[PseudoVNMSUB_VV_M1_]], [[COPY1]], [[COPY2]], -1, 6 /* e64 */, 1, implicit $vl, implicit $vtype
35 …d [[COPY2]]:vr = PseudoVSLL_VI_M1 [[COPY2]], 11, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
41 %0:vr = PseudoVNMSUB_VV_M1 %0, %1, killed %2, -1, 6, 1, implicit $vl, implicit $vtype
43 %3:vr = PseudoVSLL_VI_M1 %3, 11, $noreg, 6, implicit $vl, implicit $vtype
H A Demergency-slot.mir90 … renamable $x15 = PseudoVSETIVLI 1, 72 /* e16, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
91 …e $v25 = PseudoVMV_V_X_M1 killed renamable $x12, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype
132 …d renamable $x13 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
144 …, killed renamable $v0, killed renamable $x13, $noreg, 3 /* e8 */, 1, implicit $vl, implicit $vtype
145 … renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3 /* e8 */, implicit $vl, implicit $vtype
177 dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype
178 … renamable $v25 = PseudoVMV_V_X_M1 killed renamable $x12, $noreg, 4, implicit $vl, implicit $vtype
208 dead renamable $x13 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype
211 …mable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3, 1, implicit $vl, implicit $vtype
212 renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3, implicit $vl, implicit $vtype
H A Dwrong-stack-offset-for-rvv-object.mir170 …EXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype
171 ; CHECK-NEXT: renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3 /* e8 */, implicit $vl, implicit $vtype
186 …EXT: dead $x0 = PseudoVSETIVLI 2, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype
189 …lled renamable $v8, renamable $x8, 2, 3 /* e8 */, implicit $vl, implicit $vtype :: (store (s16) in…
201 dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype
202 renamable $v8 = PseudoVMV_V_I_MF8 0, 2, 3, implicit $vl, implicit $vtype
216 dead $x0 = PseudoVSETIVLI 2, 69, implicit-def $vl, implicit-def $vtype
218 …PseudoVSE8_V_MF8 killed renamable $v8, renamable $x8, 2, 3, implicit $vl, implicit $vtype :: (stor…
H A Dzvlsseg-spill.mir29 …seudoVSETVLI killed renamable $x11, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
30 …_v4_v5_v6 = PseudoVLSEG7E64_V_M1 renamable $x10, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype
H A Daddi-scalable-offset.mir43 …seudoVSETVLI killed renamable $x11, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
44 …_V_M1 killed renamable $x10, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype :: (load unknown-s…
H A Dfixed-vectors-emergency-slot.mir51 dead renamable $x15 = PseudoVSETIVLI 1, 72, implicit-def $vl, implicit-def $vtype
H A Dvsetvli-insert-crossbb.ll536 ; know the SEW/LMUL ratio for the if.end predecessor and the full vtype for
538 ; a predecessor we know the vtype for.
855 ; Deliberately change vtype - this could be an unknown call, but the broader
H A Dvsetvli-insert.ll411 ; Incompatible vtype
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dearly-clobber-tied-def-subreg-liveness.mir141 ; CHECK-NEXT: 48B dead $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
145 ; CHECK-NEXT: 112B %5:vr = PseudoVLE8_V_M1 %4:gpr, 2, 3, implicit $vl, implicit $vtype
157 ; CHECK-NEXT: 304B $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
161 ; CHECK-NEXT: 368B $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
165 ; CHECK-NEXT: 432B $x0 = PseudoVSETIVLI 2, 9, implicit-def $vl, implicit-def $vtype
178 %5:vr = PseudoVLE8_V_M1 %4, 2, 3 /* e8 */, implicit $vl, implicit $vtype
190 $x0 = PseudoVSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
193 %18:vrm2 = PseudoVLE16_V_M2 %17, 2, 4 /* e16 */, implicit $vl, implicit $vtype
194 $x0 = PseudoVSETIVLI 2, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
198 $x0 = PseudoVSETIVLI 2, 9 /* e16, m2, tu, mu */, implicit-def $vl, implicit-def $vtype
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/
H A Drvv-user-csr-names.s87 # vtype
89 # CHECK-INST: csrrs t1, vtype, zero
91 # CHECK-INST-ALIAS: csrr t1, vtype
93 # CHECK-INST: csrrs t2, vtype, zero
95 # CHECK-INST-ALIAS: csrr t2, vtype
97 csrrs t1, vtype, zero
/llvm-project-15.0.7/llvm/test/MC/RISCV/rvv/
H A Dsnippet.s8 vsetvli a3, a0, e16,m4,ta,ma # vtype = 16-bit integer vectors
/llvm-project-15.0.7/mlir/lib/Conversion/VectorToLLVM/
H A DConvertVectorToLLVM.cpp242 auto vtype = this->typeConverter->convertType(loadOrStoreOp.getVectorType()) in matchAndRewrite() local
246 Value ptr = castDataPtr(rewriter, loc, dataPtr, memRefTy, vtype); in matchAndRewrite()
248 replaceLoadOrStoreOp(loadOrStoreOp, adaptor, vtype, ptr, align, rewriter); in matchAndRewrite()
334 auto vtype = typeConverter->convertType(expand.getVectorType()); in matchAndRewrite() local
339 expand, vtype, ptr, adaptor.getMask(), adaptor.getPassThru()); in matchAndRewrite()
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td457 def VTYPE : RISCVReg<0, "vtype", ["vtype"]>;
H A DRISCVSystemOperands.td356 def : SysReg<"vtype", 0xC21>;
H A DRISCVInstrInfoVPseudos.td34 // X0 | X0 | Value in vl | Keep current vl, just change vtype.
76 bits<3> value = lmul; // This is encoded as the vlmul field of vtype.
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstrVSX.td210 RegisterOperand vtype, list<dag> pattern>
211 : XX2_RD6_XO5_RS6<opcode, xo2, xo, (outs vtype:$XT), (ins vtype:$XB),
263 RegisterOperand vtype, list<dag> pattern>
264 : XX1Form_memOp<opcode, xo, (outs vtype:$XT), (ins memrr:$src),
269 RegisterOperand vtype, list<dag> pattern>
270 : XX1Form_memOp<opcode, xo, (outs), (ins vtype:$XT, memrr:$dst),