| /llvm-project-15.0.7/clang/test/CodeGen/VE/ |
| H A D | ve-velintrin.c | 11 __vr vr1, vr2, vr3, vr4; variable
5340 vr2 = _vel_vrcpd_vvl(vr1, 256); in test_vrcpd_vvl()
5354 vr2 = _vel_vrcps_vvl(vr1, 256); in test_vrcps_vvl()
5368 vr2 = _vel_pvrcp_vvl(vr1, 256); in test_pvrcp_vvl()
5676 vr2 = _vel_vcvtld_vvl(vr1, 256); in test_vcvtld_vvl()
5718 vr2 = _vel_vcvtdw_vvl(vr1, 256); in test_vcvtdw_vvl()
5732 vr2 = _vel_vcvtsw_vvl(vr1, 256); in test_vcvtsw_vvl()
5760 vr2 = _vel_vcvtdl_vvl(vr1, 256); in test_vcvtdl_vvl()
5774 vr2 = _vel_vcvtds_vvl(vr1, 256); in test_vcvtds_vvl()
5788 vr2 = _vel_vcvtsd_vvl(vr1, 256); in test_vcvtsd_vvl()
[all …]
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| /llvm-project-15.0.7/llvm/test/MC/CSKY/ |
| H A D | fpuv3.s | 7 # CHECK-ASM-AND-OBJ: fldm.32 vr1-vr2, (a1)
9 fldm.32 vr1-vr2, (a1)
11 # CHECK-ASM-AND-OBJ: fldm.64 vr1-vr2, (a1)
13 fldm.64 vr1-vr2, (a1)
15 # CHECK-ASM-AND-OBJ: fstm.32 vr1-vr2, (a1)
17 fstm.32 vr1-vr2, (a1)
19 # CHECK-ASM-AND-OBJ: fstm.64 vr1-vr2, (a1)
21 fstm.64 vr1-vr2, (a1)
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| H A D | fpuv2.s | 7 # CHECK-ASM-AND-OBJ: fldms vr1-vr2, (a1)
9 fldms vr1-vr2, (a1)
11 # CHECK-ASM-AND-OBJ: fldmd vr1-vr2, (a1)
13 fldmd vr1-vr2, (a1)
15 # CHECK-ASM-AND-OBJ: fstms vr1-vr2, (a1)
17 fstms vr1-vr2, (a1)
19 # CHECK-ASM-AND-OBJ: fstmd vr1-vr2, (a1)
21 fstmd vr1-vr2, (a1)
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| /llvm-project-15.0.7/llvm/test/CodeGen/CSKY/ |
| H A D | inline-asm-f-constraint-f.ll | 33 ; CSKYF-NEXT: flds vr2, (a0, 0)
36 ; CSKYF-NEXT: fadds vr0, vr1, vr2
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| H A D | inline-asm-d-constraint-f.ll | 35 ; CSKYF-NEXT: fmovd vr2, vr0
37 ; CSKYF-NEXT: faddd vr1, vr2, vr3
|
| /llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/ |
| H A D | aix-vector-stack.ll | 9 define dso_local <4 x i32> @vec_callee_stack(<4 x i32> %vr2, <4 x i32> %vr3, <4 x i32> %vr4, <4 x i…
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| /llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/ |
| H A D | llvm.amdgcn.raw.buffer.load.ll | 209 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
212 %r3 = extractelement <2 x float> %vr2, i32 0
213 %r4 = extractelement <2 x float> %vr2, i32 1
229 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a2, i32 0, i32 0)
232 %r3 = extractelement <2 x float> %vr2, i32 0
233 %r4 = extractelement <2 x float> %vr2, i32 1
264 %vr2 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 12, i32 0, i32 0)
267 %r3 = extractelement <2 x float> %vr2, i32 0
268 %r4 = extractelement <2 x float> %vr2, i32 1
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| H A D | llvm.amdgcn.buffer.load.ll | 187 …%vr2 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 %a2, i1 0, i1 0)
190 %r3 = extractelement <2 x float> %vr2, i32 0
191 %r4 = extractelement <2 x float> %vr2, i32 1
237 %vr2 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 12, i1 0, i1 0)
240 %r3 = extractelement <2 x float> %vr2, i32 0
241 %r4 = extractelement <2 x float> %vr2, i32 1
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| /llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/ |
| H A D | RegisterInfos_ppc64.h | 142 DEFINE_VMX_PPC64(vr2, LLDB_INVALID_REGNUM), \
277 uint32_t vr2[4]; member
|
| H A D | RegisterInfos_ppc64le.h | 153 DEFINE_VMX(vr2, LLDB_INVALID_REGNUM), \
355 uint32_t vr2[4]; member
|
| /llvm-project-15.0.7/llvm/lib/Target/CSKY/ |
| H A D | CSKYRegisterInfo.td | 105 def F2_32 : CSKYFReg32<2, "fr2", ["vr2"]>, DwarfRegNum<[34]>;
|