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Searched refs:vr1 (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/clang/test/CodeGen/VE/
H A Dve-velintrin.c26 vr1 = _vel_vld_vssvl(idx, p, vr1, 256); in test_vld_vssvl()
40 vr1 = _vel_vldnc_vssvl(idx, p, vr1, 256); in test_vldnc_vssvl()
54 vr1 = _vel_vldu_vssvl(idx, p, vr1, 256); in test_vldu_vssvl()
68 vr1 = _vel_vldunc_vssvl(idx, p, vr1, 256); in test_vldunc_vssvl()
82 vr1 = _vel_vldlsx_vssvl(idx, p, vr1, 256); in test_vldlsx_vssvl()
593 vr1 = _vel_lsv_vvss(vr1, idx, v1); in test_lsv_vvss()
677 vr1 = _vel_vbrdl_vsvl(v1, vr1, 256); in test_vbrdl_vsvl()
719 vr1 = _vel_vbrdw_vsvl(v1, vr1, 256); in test_vbrdw_vsvl()
754 vr1 = _vel_vmv_vsvl(v1, vr1, 256); in test_vmv_vsvl()
3141 vr1 = _vel_vseq_vvl(vr1, 256); in test_vseq_vvl()
[all …]
/llvm-project-15.0.7/llvm/test/MC/CSKY/
H A Dfpuv2.s7 # CHECK-ASM-AND-OBJ: fldms vr1-vr2, (a1)
9 fldms vr1-vr2, (a1)
11 # CHECK-ASM-AND-OBJ: fldmd vr1-vr2, (a1)
13 fldmd vr1-vr2, (a1)
15 # CHECK-ASM-AND-OBJ: fstms vr1-vr2, (a1)
17 fstms vr1-vr2, (a1)
19 # CHECK-ASM-AND-OBJ: fstmd vr1-vr2, (a1)
21 fstmd vr1-vr2, (a1)
26 fldms vr1-vr33, (a1) # CHECK: :[[#@LINE]]:12: error: invalid register
28 fstms vr1-vr33, (a1) # CHECK: :[[#@LINE]]:12: error: invalid register
[all …]
H A Dfpuv3.s7 # CHECK-ASM-AND-OBJ: fldm.32 vr1-vr2, (a1)
9 fldm.32 vr1-vr2, (a1)
11 # CHECK-ASM-AND-OBJ: fldm.64 vr1-vr2, (a1)
13 fldm.64 vr1-vr2, (a1)
15 # CHECK-ASM-AND-OBJ: fstm.32 vr1-vr2, (a1)
17 fstm.32 vr1-vr2, (a1)
19 # CHECK-ASM-AND-OBJ: fstm.64 vr1-vr2, (a1)
21 fstm.64 vr1-vr2, (a1)
26 fstm.32 vr1-vr33, (a1) # CHECK: :[[#@LINE]]:14: error: invalid register
27 fstm.64 vr1-vr33, (a1) # CHECK: :[[#@LINE]]:14: error: invalid register
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/CSKY/fpu/
H A Dbase-f.ll11 ; CHECK-SF-NEXT: fadds vr0, vr1, vr0
29 ; CHECK-SF-NEXT: fmtvrl vr1, a0
30 ; CHECK-SF-NEXT: fadds vr0, vr0, vr1
36 ; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
51 ; CHECK-SF-NEXT: fmtvrl vr1, a0
91 ; CHECK-SF-NEXT: fmtvrl vr1, a0
113 ; CHECK-SF-NEXT: fmtvrl vr1, a0
152 ; CHECK-SF-NEXT: fmtvrl vr1, a0
174 ; CHECK-SF-NEXT: fmtvrl vr1, a0
214 ; CHECK-SF-NEXT: fmtvrl vr1, a0
[all …]
H A Dcmp-d.ll14 ; CHECK-DF-NEXT: fcmpuod vr1, vr0
16 ; CHECK-DF-NEXT: fcmpned vr1, vr0
23 ; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
25 ; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
40 ; CHECK-DF-NEXT: fldd vr1, (a0, 0)
41 ; CHECK-DF-NEXT: fcmpuod vr0, vr1
43 ; CHECK-DF-NEXT: fcmpned vr0, vr1
79 ; CHECK-DF-NEXT: fcmpned vr1, vr0
100 ; CHECK-DF-NEXT: fcmpned vr0, vr1
132 ; CHECK-DF-NEXT: fcmphsd vr0, vr1
[all …]
H A Dcmp-f.ll11 ; CHECK-SF-NEXT: fcmpuos vr1, vr0
13 ; CHECK-SF-NEXT: fcmpnes vr1, vr0
20 ; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
22 ; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
36 ; CHECK-SF-NEXT: fmtvrl vr1, a0
37 ; CHECK-SF-NEXT: fcmpnes vr0, vr1
89 ; CHECK-SF-NEXT: fcmpnes vr1, vr0
108 ; CHECK-SF-NEXT: fmtvrl vr1, a0
170 ; CHECK-SF-NEXT: fmtvrl vr1, a0
236 ; CHECK-SF-NEXT: fmtvrl vr1, a0
[all …]
H A Dbase-d.ll9 ; CHECK-DF-NEXT: faddd vr0, vr1, vr0
14 ; CHECK-DF2-NEXT: fadd.64 vr0, vr1, vr0
25 ; CHECK-DF-NEXT: fldd vr1, (a0, 0)
26 ; CHECK-DF-NEXT: faddd vr0, vr0, vr1
52 ; CHECK-DF-NEXT: fsubd vr0, vr1, vr0
70 ; CHECK-DF-NEXT: fldd vr1, (a0, 0)
71 ; CHECK-DF-NEXT: faddd vr0, vr0, vr1
99 ; CHECK-DF-NEXT: fmuld vr0, vr1, vr0
116 ; CHECK-DF-NEXT: fldd vr1, (a0, 0)
117 ; CHECK-DF-NEXT: fmuld vr0, vr0, vr1
[all …]
H A Dselect.ll12 ; CHECK-NEXT: fmovs vr1, vr0
14 ; CHECK-NEXT: fmovs vr0, vr1
20 ; CHECK-DF3-NEXT: fsel.32 vr0, vr1, vr0
31 ; GENERIC-NEXT: fmovs vr1, vr0
33 ; GENERIC-NEXT: fmovs vr0, vr1
47 ; CHECK-NEXT: fmovd vr1, vr0
49 ; CHECK-NEXT: fmovd vr0, vr1
55 ; CHECK-DF3-NEXT: fsel.64 vr0, vr1, vr0
66 ; GENERIC-NEXT: fmovd vr1, vr0
68 ; GENERIC-NEXT: fmovd vr0, vr1
H A Dbr-d.ll11 ; CHECK-DF-NEXT: fcmpned vr1, vr0
22 ; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
45 ; CHECK-DF-NEXT: fldd vr1, (a0, 0)
46 ; CHECK-DF-NEXT: fcmpned vr0, vr1
91 ; CHECK-DF-NEXT: fldd vr1, (a0, 0)
92 ; CHECK-DF-NEXT: fcmpned vr0, vr1
137 ; CHECK-DF-NEXT: fcmpuod vr1, vr0
139 ; CHECK-DF-NEXT: fcmpned vr1, vr0
182 ; CHECK-DF-NEXT: fcmpuod vr0, vr1
184 ; CHECK-DF-NEXT: fcmpned vr0, vr1
[all …]
H A Dfloat-abi.ll9 ; CHECK-NEXT: fmtvrl vr1, a0
10 ; CHECK-NEXT: fadds vr0, vr0, vr1
23 ; CHECK-NEXT: fmtvrl vr1, a2
24 ; CHECK-NEXT: fmtvrh vr1, a3
25 ; CHECK-NEXT: faddd vr0, vr1, vr0
H A Dbr-f.ll10 ; CHECK-SF-NEXT: fcmpnes vr1, vr0
21 ; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
43 ; CHECK-SF-NEXT: fmtvrl vr1, a0
44 ; CHECK-SF-NEXT: fcmpnes vr0, vr1
111 ; CHECK-SF-NEXT: fcmpuos vr1, vr0
113 ; CHECK-SF-NEXT: fcmpnes vr1, vr0
154 ; CHECK-SF-NEXT: fmtvrl vr1, a0
155 ; CHECK-SF-NEXT: fcmpnes vr0, vr1
275 ; CHECK-SF-NEXT: fmtvrl vr1, a0
376 ; CHECK-SF-NEXT: fmtvrl vr1, a0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/CSKY/
H A Dinline-asm-f-constraint-f.ll12 ; CSKYF-NEXT: flds vr1, (a0, 0)
14 ; CSKYF-NEXT: fadds vr0, vr0, vr1
34 ; CSKYF-NEXT: fmovs vr1, vr0
36 ; CSKYF-NEXT: fadds vr0, vr1, vr2
H A Dinline-asm-d-constraint-f.ll12 ; CSKYF-NEXT: fldd vr1, (a0, 0)
14 ; CSKYF-NEXT: faddd vr0, vr0, vr1
37 ; CSKYF-NEXT: faddd vr1, vr2, vr3
39 ; CSKYF-NEXT: fmovd vr0, vr1
H A Dinline-asm-float-abi-names.ll17 ; CSKYIFD-NEXT: fmovd vr0, vr1
31 ; CSKYIFD-NEXT: fmovd vr0, vr1
45 ; CSKYIFD-NEXT: fstod vr0, vr1
59 ; CSKYIFD-NEXT: fstod vr0, vr1
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dllvm.amdgcn.buffer.load.ll186 …%vr1 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 %a1, i1 0, i1 0)
188 %r1 = extractelement <2 x float> %vr1, i32 0
189 %r2 = extractelement <2 x float> %vr1, i32 1
206 %r1 = extractelement <2 x float> %vr1, i32 0
207 %r2 = extractelement <2 x float> %vr1, i32 1
236 %vr1 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0)
238 %r1 = extractelement <2 x float> %vr1, i32 0
239 %r2 = extractelement <2 x float> %vr1, i32 1
252 %vr1 = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 0, i32 4, i1 0, i1 0)
254 %r1 = extractelement <2 x float> %vr1, i32 0
[all …]
H A Dllvm.amdgcn.raw.buffer.load.ll208 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
210 %r1 = extractelement <2 x float> %vr1, i32 0
211 %r2 = extractelement <2 x float> %vr1, i32 1
228 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 %a1, i32 0, i32 0)
230 %r1 = extractelement <2 x float> %vr1, i32 0
231 %r2 = extractelement <2 x float> %vr1, i32 1
263 %vr1 = call <2 x float> @llvm.amdgcn.raw.buffer.load.v2f32(<4 x i32> %rsrc, i32 4, i32 0, i32 0)
265 %r1 = extractelement <2 x float> %vr1, i32 0
266 %r2 = extractelement <2 x float> %vr1, i32 1
/llvm-project-15.0.7/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64.h141 DEFINE_VMX_PPC64(vr1, LLDB_INVALID_REGNUM), \
276 uint32_t vr1[4]; member
H A DRegisterInfos_ppc64le.h152 DEFINE_VMX(vr1, LLDB_INVALID_REGNUM), \
354 uint32_t vr1[4]; member
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td104 def F1_32 : CSKYFReg32<1, "fr1", ["vr1"]>, DwarfRegNum<[33]>;