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/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dinline-asm.ll13 …%0 = tail call <vscale x 1 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 1 x i1> %in, …
25 …%0 = tail call <vscale x 2 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i1> %in, …
37 …%0 = tail call <vscale x 4 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 4 x i1> %in, …
49 …%0 = tail call <vscale x 8 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 8 x i1> %in, …
61 …%0 = tail call <vscale x 16 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 16 x i1> %in…
73 …%0 = tail call <vscale x 32 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 32 x i1> %in…
85 …%0 = tail call <vscale x 64 x i1> asm "vmand.mm $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 64 x i1> %in…
97 …%0 = tail call <vscale x 1 x i64> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 1 x i64> %in,…
109 …%0 = tail call <vscale x 2 x i64> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 2 x i64> %in,…
121 …%0 = tail call <vscale x 4 x i64> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(<vscale x 4 x i64> %in,…
[all …]
H A Dvsetvli-insert.mir103 - { id: 0, class: vr }
104 - { id: 1, class: vr }
106 - { id: 3, class: vr }
129 %1:vr = COPY $v9
130 %0:vr = COPY $v8
142 - { id: 1, class: vr }
169 %1:vr = COPY $v8
238 %0:vr = COPY $v8
360 %1:vr = COPY $v9
361 %0:vr = COPY $v8
[all …]
H A Dvsetvli-insert-crossbb.mir225 %6:vr = COPY $v8
386 %5:vr = COPY $v9
387 %4:vr = COPY $v8
464 %6:vr = COPY $v9
465 %5:vr = COPY $v8
627 %7:vr = PseudoVADD_VX_M1 %4:vr, %6:gpr, -1, 6
699 %7:vr = PseudoVADD_VX_M1 %4:vr, %6:gpr, -1, 6
794 %12:vr = COPY %11
795 %10:vr = COPY %12
875 %t1:vr = COPY $v1
[all …]
H A Dcommuted-op-indices-regression.mir20 - { id: 0, class: vr, preferred-register: '' }
23 - { id: 3, class: vr, preferred-register: '' }
30 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v0
33 …; CHECK-NEXT: [[PseudoVNMSUB_VV_M1_:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[PseudoVNMSUB_VV_M1_]], [[C…
34 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVNMSUB_VV_M1_]]
35 …; CHECK-NEXT: dead [[COPY2]]:vr = PseudoVSLL_VI_M1 [[COPY2]], 11, $noreg, 6 /* e64 */, implicit $v…
38 %0:vr = COPY $v0
41 %0:vr = PseudoVNMSUB_VV_M1 %0, %1, killed %2, -1, 6, 1, implicit $vl, implicit $vtype
42 %3:vr = COPY %0
43 %3:vr = PseudoVSLL_VI_M1 %3, 11, $noreg, 6, implicit $vl, implicit $vtype
H A Dmask-reg-alloc.mir25 %0:vr = COPY $v0
26 %1:vr = COPY $v1
27 %2:vr = COPY $v2
28 %3:vr = COPY $v3
33 %8:vr = PseudoVADD_VV_M1 killed %5, killed %7, 1, 3
H A Dpass-fast-math-flags-sdnode.ll12 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v0
13 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v9
14 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY $v8
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dfold-load-binops.ll23 %vr = insertelement <4 x float> %va, float %r, i32 0
24 ret <4 x float> %vr
41 ret <2 x double> %vr
57 %vr = insertelement <4 x float> %va, float %r, i32 0
58 ret <4 x float> %vr
75 ret <2 x double> %vr
91 %vr = insertelement <4 x float> %va, float %r, i32 0
92 ret <4 x float> %vr
109 ret <2 x double> %vr
126 ret <4 x float> %vr
[all …]
H A Davx512fp16-fold-load-binops.ll16 %vr = insertelement <8 x half> %va, half %r, i32 0
17 ret <8 x half> %vr
28 %vr = insertelement <8 x half> %va, half %r, i32 0
29 ret <8 x half> %vr
40 %vr = insertelement <8 x half> %va, half %r, i32 0
41 ret <8 x half> %vr
52 %vr = insertelement <8 x half> %va, half %r, i32 0
53 ret <8 x half> %vr
65 %vr = insertelement <8 x half> %va, half %r, i32 0
66 ret <8 x half> %vr
[all …]
H A Dfma4-scalar-memfold.ll28 %vr = call <4 x float> @llvm.x86.fma4.vfmadd.ss(<4 x float> %av, <4 x float> %av, <4 x float> %bv)
30 %sr = extractelement <4 x float> %vr, i32 0
54 %vr = call <4 x float> @llvm.x86.fma4.vfmadd.ss(<4 x float> %av, <4 x float> %bv, <4 x float> %av)
56 %sr = extractelement <4 x float> %vr, i32 0
76 …%vr = call <2 x double> @llvm.x86.fma4.vfmadd.sd(<2 x double> %av, <2 x double> %av, <2 x double> …
78 %sr = extractelement <2 x double> %vr, i32 0
98 …%vr = call <2 x double> @llvm.x86.fma4.vfmadd.sd(<2 x double> %av, <2 x double> %bv, <2 x double> …
100 %sr = extractelement <2 x double> %vr, i32 0
H A Dfma-scalar-memfold.ll49 %sr = extractelement <4 x float> %vr, i32 0
86 %sr = extractelement <4 x float> %vr, i32 0
123 %sr = extractelement <4 x float> %vr, i32 0
160 %sr = extractelement <4 x float> %vr, i32 0
197 %sr = extractelement <4 x float> %vr, i32 0
234 %sr = extractelement <4 x float> %vr, i32 0
271 %sr = extractelement <4 x float> %vr, i32 0
308 %sr = extractelement <4 x float> %vr, i32 0
341 %sr = extractelement <2 x double> %vr, i32 0
374 %sr = extractelement <2 x double> %vr, i32 0
[all …]
/llvm-project-15.0.7/flang/unittests/Evaluate/
H A Dreal.cpp77 ValueWithRealFlags<R> vr; in basicTests() local
79 TEST(vr.flags.empty())(desc); in basicTests() local
136 vr = R::FromInteger(ix, rounding); in basicTests()
139 TEST(!vr.value.IsZero())(ldesc); in basicTests() local
147 TEST(vr.flags.empty())(ldesc); in basicTests() local
165 TEST(vr.value.ToWholeNumber().value.Compare(vr.value) == Relation::Equal) in basicTests() local
173 vr = R::FromInteger(ix); in basicTests()
174 TEST(vr.value.IsNegative())(ldesc); in basicTests() local
176 TEST(!vr.value.IsZero())(ldesc); in basicTests() local
184 TEST(vr.flags.empty())(ldesc); in basicTests() local
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-xlcompat-fnabs.ll3 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 < %s | \
6 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
9 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
12 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s \
15 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mattr=+vsx < %s | \
19 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
22 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr6 < %s | \
25 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
28 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -mcpu=pwr8 \
H A Dscalar_vector_test_5.ll2 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
4 ; RUN: llc -mcpu=pwr9 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
6 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
8 ; RUN: llc -mcpu=pwr8 -verify-machineinstrs -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
H A Dload-v4i8-improved.ll3 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck --check-prefix=CHECK-LE \
6 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
9 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
12 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names | FileCheck \
H A Dload-rightmost-vector-elt.ll3 ; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
7 ; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
11 ; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
15 ; RUN: -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
H A Dspill_p9_setb.ll5 ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
8 ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr9 < %s \
11 ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
14 ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
H A Dvsx-spill.ll2 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
4 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
7 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
9 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | \
11 ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr \
14 ; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck \
H A Dpcrel-linkeropt-option.ll3 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
6 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
9 ; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
/llvm-project-15.0.7/llvm/test/CodeGen/VE/Vector/
H A Dvp_fsub_merge.ll14 …%vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
15 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
28 …%vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
29 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
45 …%vr = call <256 x float> @llvm.vp.fsub.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
46 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
61 …%vr = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1>…
62 …%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double>…
75 …%vr = call <256 x double> @llvm.vp.fsub.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1>…
76 …%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double>…
[all …]
H A Dvp_fmul_merge.ll14 …%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
15 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
28 …%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
29 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
42 …%vr = call <256 x float> @llvm.vp.fmul.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
43 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
58 …%vr = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1>…
59 …%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double>…
72 …%vr = call <256 x double> @llvm.vp.fmul.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1>…
73 …%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double>…
[all …]
H A Dvp_fdiv_merge.ll14 …%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
15 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
28 …%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
29 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
42 …%vr = call <256 x float> @llvm.vp.fdiv.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
43 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
58 …%vr = call <256 x double> @llvm.vp.fdiv.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1>…
59 …%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double>…
72 …%vr = call <256 x double> @llvm.vp.fdiv.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1>…
73 …%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double>…
[all …]
H A Dvp_fadd_merge.ll14 …%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
15 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
28 …%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
29 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
42 …%vr = call <256 x float> @llvm.vp.fadd.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x i1> %m…
43 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
58 …%vr = call <256 x double> @llvm.vp.fadd.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1>…
59 …%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double>…
72 …%vr = call <256 x double> @llvm.vp.fadd.v256f64(<256 x double> %i0, <256 x double> %i1, <256 x i1>…
73 …%r0 = call <256 x double> @llvm.vp.merge.v256f64(<256 x i1> %m, <256 x double> %vr, <256 x double>…
[all …]
H A Dvp_fma_merge.ll17 …%vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> …
18 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
34 …%vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> …
35 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
51 …%vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> …
52 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
68 …%vr = call <256 x float> @llvm.vp.fma.v256f32(<256 x float> %i0, <256 x float> %i1, <256 x float> …
69 …%r0 = call <256 x float> @llvm.vp.merge.v256f32(<256 x i1> %m, <256 x float> %vr, <256 x float> %p…
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dbuiltins-hexagon-v66-128B.c58 HEXAGON_Vect2048 vr; in test28() local
64 vr = *p2; in test28()
66 return __builtin_HEXAGON_V6_vasr_into_128B(vr, v1, v2); in test28()
H A Dbuiltins-hexagon-v66.c82 HEXAGON_Vect1024 vr; in test8() local
88 vr = *p2; in test8()
90 return __builtin_HEXAGON_V6_vasr_into(vr, v1, v2); in test8()

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