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/llvm-project-15.0.7/libcxx/test/std/utilities/allocator.adaptor/allocator.adaptor.types/
H A Dallocator_pointers.pass.cpp46 static_assert(std::is_same<bool, decltype( vp == vp)>::value, ""); in test_pointer()
47 static_assert(std::is_same<bool, decltype( vp != vp)>::value, ""); in test_pointer()
48 static_assert(std::is_same<bool, decltype( vp > vp)>::value, ""); in test_pointer()
49 static_assert(std::is_same<bool, decltype( vp >= vp)>::value, ""); in test_pointer()
50 static_assert(std::is_same<bool, decltype( vp < vp)>::value, ""); in test_pointer()
51 static_assert(std::is_same<bool, decltype( vp <= vp)>::value, ""); in test_pointer()
83 static_assert(std::is_same<bool, decltype( vp == vp)>::value, ""); in test_void_pointer()
84 static_assert(std::is_same<bool, decltype( vp != vp)>::value, ""); in test_void_pointer()
85 static_assert(std::is_same<bool, decltype( vp > vp)>::value, ""); in test_void_pointer()
86 static_assert(std::is_same<bool, decltype( vp >= vp)>::value, ""); in test_void_pointer()
[all …]
/llvm-project-15.0.7/libcxx/test/std/utilities/memory/default.allocator/
H A Dallocator_pointers.pass.cpp45 static_assert(std::is_same<bool, decltype( vp == vp)>::value, ""); in test_pointer()
46 static_assert(std::is_same<bool, decltype( vp != vp)>::value, ""); in test_pointer()
47 static_assert(std::is_same<bool, decltype( vp > vp)>::value, ""); in test_pointer()
48 static_assert(std::is_same<bool, decltype( vp >= vp)>::value, ""); in test_pointer()
49 static_assert(std::is_same<bool, decltype( vp < vp)>::value, ""); in test_pointer()
50 static_assert(std::is_same<bool, decltype( vp <= vp)>::value, ""); in test_pointer()
82 static_assert(std::is_same<bool, decltype( vp == vp)>::value, ""); in test_void_pointer()
83 static_assert(std::is_same<bool, decltype( vp != vp)>::value, ""); in test_void_pointer()
84 static_assert(std::is_same<bool, decltype( vp > vp)>::value, ""); in test_void_pointer()
85 static_assert(std::is_same<bool, decltype( vp >= vp)>::value, ""); in test_void_pointer()
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/PowerPC/
H A Dbuiltins-ppc-pair-mma.c16 __vector_pair vp = *((__vector_pair *)vpp); in test1() local
223 __builtin_mma_xvf64ger(&vq, vp, vc); in test14()
1053 __builtin_vsx_stxvp(vp, 0L, vp2); in test66()
1068 __builtin_vsx_stxvp(vp, offset, vp2); in test67()
1083 __builtin_vsx_stxvp(vp, 18L, vp2); in test68()
1098 __builtin_vsx_stxvp(vp, 1L, vp2); in test69()
1113 __builtin_vsx_stxvp(vp, 42L, vp2); in test70()
1245 __builtin_mma_stxvp(vp, 0L, vp2); in test78()
1275 __builtin_mma_stxvp(vp, 18L, vp2); in test80()
1290 __builtin_mma_stxvp(vp, 1L, vp2); in test81()
[all …]
/llvm-project-15.0.7/llvm/test/Verifier/
H A Dvp-intrinsics.ll103 declare i32 @llvm.vp.reduce.add.v8i32(i32, <8 x i32>, <8 x i1>, i32)
104 declare i32 @llvm.vp.reduce.mul.v8i32(i32, <8 x i32>, <8 x i1>, i32)
105 declare i32 @llvm.vp.reduce.and.v8i32(i32, <8 x i32>, <8 x i1>, i32)
106 declare i32 @llvm.vp.reduce.or.v8i32(i32, <8 x i32>, <8 x i1>, i32)
107 declare i32 @llvm.vp.reduce.xor.v8i32(i32, <8 x i32>, <8 x i1>, i32)
108 declare i32 @llvm.vp.reduce.smax.v8i32(i32, <8 x i32>, <8 x i1>, i32)
109 declare i32 @llvm.vp.reduce.smin.v8i32(i32, <8 x i32>, <8 x i1>, i32)
110 declare i32 @llvm.vp.reduce.umax.v8i32(i32, <8 x i32>, <8 x i1>, i32)
111 declare i32 @llvm.vp.reduce.umin.v8i32(i32, <8 x i32>, <8 x i1>, i32)
124 declare <8 x i64> @llvm.vp.zext.v8i64.v8i32(<8 x i32>, <8 x i1>, i32)
[all …]
H A Dinvalid-vp-intrinsics.ll3 declare <4 x i32> @llvm.vp.fptosi.v4i32.v8f32(<8 x float>, <4 x i1>, i32)
4 declare <4 x i1> @llvm.vp.fcmp.v4f32(<4 x float>, <4 x float>, metadata, <4 x i1>, i32)
5 declare <4 x i1> @llvm.vp.icmp.v4i32(<4 x i32>, <4 x i32>, metadata, <4 x i1>, i32)
11 %r0 = call <4 x i32> @llvm.vp.fptosi.v4i32.v8f32(<8 x float> %src, <4 x i1> %m, i32 %n)
16 ; CHECK-NEXT: %r0 = call <4 x i1> @llvm.vp.fcmp.v4f32
18 ; CHECK-NEXT: %r1 = call <4 x i1> @llvm.vp.fcmp.v4f32
22 …%r1 = call <4 x i1> @llvm.vp.fcmp.v4f32(<4 x float> %a, <4 x float> %b, metadata !"eq", <4 x i1> %…
27 ; CHECK-NEXT: %r0 = call <4 x i1> @llvm.vp.icmp.v4i32
29 ; CHECK-NEXT: %r1 = call <4 x i1> @llvm.vp.icmp.v4i32
32 …%r0 = call <4 x i1> @llvm.vp.icmp.v4i32(<4 x i32> %a, <4 x i32> %b, metadata !"bad", <4 x i1> %m, …
[all …]
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dppc-pair-mma-types.cpp212 *vpp = vp; in testVPArg1()
213 *vpp1 = vp; in testVPArg1()
217 *vpp = vp; in testVPArg2()
218 *vpp2 = vp; in testVPArg2()
222 *vpp = *vp; in testVPArg3()
227 *vpp = *vp; in testVPArg4()
237 *vpp = vp; in testVPArg6()
238 *vpp2 = vp; in testVPArg6()
242 *vpp = *vp; in testVPArg7()
328 __vector_pair vp; in testVPTemplate() local
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dvplan-sink-scalars-and-merge.ll254 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule vp<[[WIDE_CAN_IV]]> vp<[[BTC]]>
262 ; CHECK-NEXT: EMIT vp<[[MASK2:%.+]]> = select vp<[[MASK]]> vp<[[NOT2]]> ir<false>
358 ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]> vp<[[NOT]]> ir<false>
359 ; CHECK-NEXT: BLEND %p = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]>
360 ; CHECK-NEXT: EMIT vp<[[OR:%.+]]> = or vp<[[MASK2]]> vp<[[MASK3]]>
460 ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]> vp<[[NOT]]> ir<false>
461 ; CHECK-NEXT: BLEND %p = ir<0>/vp<[[MASK3]]> vp<[[PRED]]>/vp<[[MASK2]]>
465 ; CHECK-NEXT: EMIT vp<[[OR:%.+]]> = or vp<[[MASK2]]> vp<[[MASK3]]>
578 ; CHECK-NEXT: EMIT vp<[[MASK3:%.+]]> = select vp<[[MASK1]]> vp<[[NOT]]> ir<false>
579 ; CHECK-NEXT: EMIT vp<[[MASK4:%.+]]> = or vp<[[MASK2]]> vp<[[MASK3]]>
[all …]
H A Dfirst-order-recurrence-sink-replicate-region.ll24 ; CHECK-NEXT: vp<[[STEPS:%.]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, ir<1>
25 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
68 ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
69 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
113 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
143 ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF + vp<[[CAN_IV]]>
144 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
188 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule vp<[[WIDEN_CAN]]> vp<[[BTC]]>
265 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
361 ; CHECK-NEXT: EMIT vp<[[MASK:%.+]]> = icmp ule ir<%iv> vp<[[BTC]]>
[all …]
H A Dvplan-printing.ll20 ; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, ir<1>
26 ; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
27 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
76 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
123 ; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]> vp<[[VEC_TC]]>
234 ; CHECK-NEXT: BLEND %d = ir<0>/vp<[[NOT]]> vp<[[PRED]]>/ir<%cmp>
415 ; CHECK-NEXT: EMIT vp<[[OR1:%.+]]> = or vp<[[SEL1]]> ir<%cmp1>
438 ; CHECK-NEXT: EMIT vp<[[SEL2:%.+]]> = select vp<[[NOT1]]> vp<[[NOT2]]> ir<false>
439 ; CHECK-NEXT: BLEND %ysd.0 = vp<[[PHI]]>/vp<[[OR1]]> ir<%psd>/vp<[[SEL2]]>
499 ; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, vp<[[EXP_SCEV]]>
[all …]
H A Dinterleave-and-scalarize-only.ll16 ; DBG-NEXT: vp<[[IV_STEPS:%.]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<%start>, ir<1>
20 ; DBG-NEXT: EMIT vp<[[INC:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
21 ; DBG-NEXT: EMIT branch-on-count vp<[[INC]]> vp<[[VEC_TC]]>
72 ; DBG-NEXT: vp<[[STEPS1:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<false>, ir<true>
73 ; DBG-NEXT: vp<[[STEPS2:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<0>, ir<1>
104 ; DBG-NEXT: EMIT vp<[[CAN_IV_INC:%.+]]> = VF * UF +(nuw) vp<[[CAN_IV]]>
105 ; DBG-NEXT: EMIT branch-on-count vp<[[CAN_IV_INC]]> vp<[[VEC_TC]]>
186 ; DBG-NEXT: vp<%4> = SCALAR-STEPS vp<%2>, ir<0>, ir<1>
187 ; DBG-NEXT: EMIT vp<%5> = first-order splice ir<%for> vp<%4>
189 ; DBG-NEXT: EMIT vp<%7> = VF * UF +(nuw) vp<%2>
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Dexpand-vp.ll128 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.add}}
129 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.sub}}
130 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.mul}}
131 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.sdiv}}
132 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.srem}}
133 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.udiv}}
134 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.urem}}
135 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.and}}
136 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.or}}
137 ; ALL-CONVERT-NOT: {{call.* @llvm.vp.xor}}
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dadd_vp.ll4 declare <2 x i32> @llvm.vp.add.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
5 declare <2 x i32> @llvm.vp.sub.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
7 declare <2 x i8> @llvm.vp.add.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
8 declare <2 x i8> @llvm.vp.sub.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
27 ; %Z = sub i32 %X, %Y, vp(%mask, %evl)
28 %Z = call <2 x i32> @llvm.vp.sub.v2i32(<2 x i32> %X, <2 x i32> %Y, <2 x i1> %mask, i32 %evl)
29 ; %Q = add i32 %Z, %Y, vp(%mask, %evl)
34 ; Mixing regular SIMD with vp intrinsics (vp add match root).
42 ; %Q = add i32 %Z, %Y, vp(%mask, %evl)
47 ; Mixing regular SIMD with vp intrinsics (vp inside pattern, regular instruction root).
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dundef-vp-ops.ll9 declare <4 x i32> @llvm.vp.load.v4i32.p0v4i32(<4 x i32>*, <4 x i1>, i32)
27 declare <4 x i32> @llvm.vp.gather.v4i32.v4p0i32(<4 x i32*>, <4 x i1>, i32)
81 declare <4 x i32> @llvm.vp.add.v4i32(<4 x i32>, <4 x i32>, <4 x i1>, i32)
369 declare i32 @llvm.vp.reduce.add.v4i32(i32, <4 x i32>, <4 x i1>, i32)
387 declare i32 @llvm.vp.reduce.mul.v4i32(i32, <4 x i32>, <4 x i1>, i32)
405 declare i32 @llvm.vp.reduce.and.v4i32(i32, <4 x i32>, <4 x i1>, i32)
423 declare i32 @llvm.vp.reduce.or.v4i32(i32, <4 x i32>, <4 x i1>, i32)
441 declare i32 @llvm.vp.reduce.xor.v4i32(i32, <4 x i32>, <4 x i1>, i32)
459 declare i32 @llvm.vp.reduce.smax.v4i32(i32, <4 x i32>, <4 x i1>, i32)
477 declare i32 @llvm.vp.reduce.smin.v4i32(i32, <4 x i32>, <4 x i1>, i32)
[all …]
H A Dfixed-vectors-vpstore.ll7 declare void @llvm.vp.store.v2i8.p0v2i8(<2 x i8>, <2 x i8>*, <2 x i1>, i32)
19 declare void @llvm.vp.store.v4i8.p0v4i8(<4 x i8>, <4 x i8>*, <4 x i1>, i32)
31 declare void @llvm.vp.store.v8i8.p0v8i8(<8 x i8>, <8 x i8>*, <8 x i1>, i32)
43 declare void @llvm.vp.store.v2i16.p0v2i16(<2 x i16>, <2 x i16>*, <2 x i1>, i32)
55 declare void @llvm.vp.store.v4i16.p0v4i16(<4 x i16>, <4 x i16>*, <4 x i1>, i32)
67 declare void @llvm.vp.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, <8 x i1>, i32)
79 declare void @llvm.vp.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, <2 x i1>, i32)
91 declare void @llvm.vp.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, <4 x i1>, i32)
103 declare void @llvm.vp.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, <8 x i1>, i32)
115 declare void @llvm.vp.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, <2 x i1>, i32)
[all …]
H A Dfixed-vectors-marith-vp.ll7 declare <1 x i1> @llvm.vp.and.v1i1(<1 x i1>, <1 x i1>, <1 x i1>, i32)
19 declare <2 x i1> @llvm.vp.and.v2i1(<2 x i1>, <2 x i1>, <2 x i1>, i32)
31 declare <4 x i1> @llvm.vp.and.v4i1(<4 x i1>, <4 x i1>, <4 x i1>, i32)
43 declare <8 x i1> @llvm.vp.and.v8i1(<8 x i1>, <8 x i1>, <8 x i1>, i32)
67 declare <1 x i1> @llvm.vp.or.v1i1(<1 x i1>, <1 x i1>, <1 x i1>, i32)
79 declare <2 x i1> @llvm.vp.or.v2i1(<2 x i1>, <2 x i1>, <2 x i1>, i32)
91 declare <4 x i1> @llvm.vp.or.v4i1(<4 x i1>, <4 x i1>, <4 x i1>, i32)
103 declare <8 x i1> @llvm.vp.or.v8i1(<8 x i1>, <8 x i1>, <8 x i1>, i32)
127 declare <1 x i1> @llvm.vp.xor.v1i1(<1 x i1>, <1 x i1>, <1 x i1>, i32)
139 declare <2 x i1> @llvm.vp.xor.v2i1(<2 x i1>, <2 x i1>, <2 x i1>, i32)
[all …]
H A Dfixed-vectors-vpload.ll7 declare <2 x i8> @llvm.vp.load.v2i8.p0v2i8(<2 x i8>*, <2 x i1>, i32)
19 declare <3 x i8> @llvm.vp.load.v3i8.p0v3i8(<3 x i8>*, <3 x i1>, i32)
31 declare <4 x i8> @llvm.vp.load.v4i8.p0v4i8(<4 x i8>*, <4 x i1>, i32)
55 declare <8 x i8> @llvm.vp.load.v8i8.p0v8i8(<8 x i8>*, <8 x i1>, i32)
67 declare <2 x i16> @llvm.vp.load.v2i16.p0v2i16(<2 x i16>*, <2 x i1>, i32)
79 declare <4 x i16> @llvm.vp.load.v4i16.p0v4i16(<4 x i16>*, <4 x i1>, i32)
91 declare <8 x i16> @llvm.vp.load.v8i16.p0v8i16(<8 x i16>*, <8 x i1>, i32)
115 declare <2 x i32> @llvm.vp.load.v2i32.p0v2i32(<2 x i32>*, <2 x i1>, i32)
127 declare <4 x i32> @llvm.vp.load.v4i32.p0v4i32(<4 x i32>*, <4 x i1>, i32)
139 declare <6 x i32> @llvm.vp.load.v6i32.p0v6i32(<6 x i32>*, <6 x i1>, i32)
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dalloc-size.c28 void *const vp = my_malloc(100); in test1() local
30 gi = OBJECT_SIZE_BUILTIN(vp, 0); in test1()
32 gi = OBJECT_SIZE_BUILTIN(vp, 1); in test1()
34 gi = OBJECT_SIZE_BUILTIN(vp, 2); in test1()
36 gi = OBJECT_SIZE_BUILTIN(vp, 3); in test1()
86 void *const vp = my_malloc(gi); in test2() local
88 gi = OBJECT_SIZE_BUILTIN(vp, 0); in test2()
310 gi = OBJECT_SIZE_BUILTIN(vp, 0); in test11()
312 gi = OBJECT_SIZE_BUILTIN(vp, 1); in test11()
314 gi = OBJECT_SIZE_BUILTIN(vp, 2); in test11()
[all …]
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DVPIntrinsics.def158 // llvm.vp.add(x,y,mask,vlen)
161 // llvm.vp.and(x,y,mask,vlen)
170 // llvm.vp.mul(x,y,mask,vlen)
173 // llvm.vp.or(x,y,mask,vlen)
179 // llvm.vp.shl(x,y,mask,vlen)
185 // llvm.vp.sub(x,y,mask,vlen)
194 // llvm.vp.xor(x,y,mask,vlen)
233 // llvm.vp.fneg(x,mask,vlen)
294 // llvm.vp.zext(x,mask,vlen)
297 // llvm.vp.sext(x,mask,vlen)
[all …]
/llvm-project-15.0.7/clang/test/Sema/
H A Dbuiltins-x86_64.c11 void *vp; in call_x86_64_builtins() local
28 …(void)__builtin_ia32_fxrstor64(vp); // expected-error{{use of unkno… in call_x86_64_builtins()
29 …(void)__builtin_ia32_fxsave64(vp); // expected-error{{use of unkno… in call_x86_64_builtins()
30 …(void)__builtin_ia32_xsave64(vp, 4); // expected-error{{use of unkno… in call_x86_64_builtins()
31 …(void)__builtin_ia32_xrstor64(vp, 4); // expected-error{{use of unkno… in call_x86_64_builtins()
32 …(void)__builtin_ia32_xsaveopt64(vp, 4); // expected-error{{use of unkno… in call_x86_64_builtins()
33 …(void)__builtin_ia32_xrstors64(vp, 4); // expected-error{{use of unkno… in call_x86_64_builtins()
34 …(void)__builtin_ia32_xsavec64(vp, 4); // expected-error{{use of unkno… in call_x86_64_builtins()
35 …(void)__builtin_ia32_xsaves64(vp, 4); // expected-error{{use of unkno… in call_x86_64_builtins()
H A Dppc-pair-mma-types.c112 void testVPArg1(__vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}} in testVPArg1() argument
114 *vpp = vp; in testVPArg1()
117 void testVPArg2(const __vector_pair vp, int *ptr) { // expected-error {{invalid use of PPC MMA type… in testVPArg2() argument
119 *vpp = vp; in testVPArg2()
122 void testVPArg6(const vp_t vp, int *ptr) { // expected-error {{invalid use of PPC MMA type}} in testVPArg6() argument
124 *vpp = vp; in testVPArg6()
150 __vector_pair *vp; member
201 …__vector_pair vp = __builtin_vsx_lxvp(f, vpp); // expected-error {{passing 'float' to parameter of… in testBuiltinTypes1() local
202 …__builtin_vsx_stxvp(vp, 32799, vp2); // expected-error {{passing 'int' to parameter of i… in testBuiltinTypes1()
207 …__builtin_vsx_stxvp(vp, c, vp2); // expected-error {{passing 'unsigned char' to par… in testBuiltinTypes2()
[all …]
/llvm-project-15.0.7/compiler-rt/test/profile/Posix/
H A Dinstrprof-value-prof-shared.test2 …lang_profgen -O2 -mllvm -enable-value-profiling=true -mllvm -vp-static-alloc=true -mllvm -vp-count…
3 …lang_profgen -O2 -mllvm -enable-value-profiling=true -mllvm -vp-static-alloc=true -mllvm -vp-count…
10 // RUN: %clang_pgogen -O2 -mllvm -disable-vp=false -mllvm -vp-static-alloc=true -mllvm -vp-counters…
11 // RUN: %clang_pgogen -O2 -mllvm -disable-vp=false -mllvm -vp-static-alloc=true -mllvm -vp-counters…
23 // RUN: %clang_pgogen=%t.prof -O2 -mllvm -disable-vp=false -mllvm -vp-static-alloc=true -mllvm -vp-…
24 // RUN: %clang_pgogen=%t.prof -O2 -mllvm -disable-vp=false -mllvm -vp-static-alloc=true -mllvm -vp-…
35 // RUN: %clang_pgogen -O2 -mllvm -disable-vp=false -mllvm -vp-static-alloc=false -mllvm -vp-counter…
36 // RUN: %clang_pgogen -O2 -mllvm -disable-vp=false -mllvm -vp-static-alloc=false -mllvm -vp-counter…
45 // RUN: %clang_pgogen -O2 -mllvm -disable-vp=false -mllvm -vp-static-alloc=false -mllvm -vp-counter…
46 // RUN: %clang_pgogen -O2 -mllvm -disable-vp=false -mllvm -vp-static-alloc=true -mllvm -vp-counters…
/llvm-project-15.0.7/mlir/test/Target/LLVMIR/Import/
H A Dintrinsic.ll721 declare <8 x float> @llvm.vp.fneg.v8f32(<8 x float>, <8 x i1>, i32)
723 declare i32 @llvm.vp.reduce.add.v8i32(i32, <8 x i32>, <8 x i1>, i32)
724 declare i32 @llvm.vp.reduce.mul.v8i32(i32, <8 x i32>, <8 x i1>, i32)
725 declare i32 @llvm.vp.reduce.and.v8i32(i32, <8 x i32>, <8 x i1>, i32)
726 declare i32 @llvm.vp.reduce.or.v8i32(i32, <8 x i32>, <8 x i1>, i32)
727 declare i32 @llvm.vp.reduce.xor.v8i32(i32, <8 x i32>, <8 x i1>, i32)
728 declare i32 @llvm.vp.reduce.smax.v8i32(i32, <8 x i32>, <8 x i1>, i32)
729 declare i32 @llvm.vp.reduce.smin.v8i32(i32, <8 x i32>, <8 x i1>, i32)
730 declare i32 @llvm.vp.reduce.umax.v8i32(i32, <8 x i32>, <8 x i1>, i32)
731 declare i32 @llvm.vp.reduce.umin.v8i32(i32, <8 x i32>, <8 x i1>, i32)
[all …]
/llvm-project-15.0.7/clang/test/SemaObjC/
H A Darc-type-conversion.m47 void from_void(void *vp) {
48 __strong id *sip = (__strong id *)vp;
49 __weak id *wip = (__weak id *)vp;
50 __autoreleasing id *aip = (__autoreleasing id *)vp;
53 __strong id **sipp = (__strong id **)vp;
54 __weak id **wipp = (__weak id **)vp;
55 __autoreleasing id **aipp = (__autoreleasing id **)vp;
70 void ownership_transfer_in_cast(void *vp, Block *pblk) {
72 __weak NSString **wip = (NSString**)(__weak id *)vp;
76 __strong id **sipp = (id**)(__strong id **)vp;
[all …]
/llvm-project-15.0.7/mlir/test/Target/LLVMIR/
H A Dllvmir-intrinsics.mlir528 "llvm.intr.vp.add" (%A, %B, %mask, %evl) :
531 "llvm.intr.vp.sub" (%A, %B, %mask, %evl) :
534 "llvm.intr.vp.mul" (%A, %B, %mask, %evl) :
558 "llvm.intr.vp.or" (%A, %B, %mask, %evl) :
583 "llvm.intr.vp.fneg" (%C, %mask, %evl) :
651 "llvm.intr.vp.trunc" (%E, %mask, %evl) :
654 "llvm.intr.vp.zext" (%A, %mask, %evl) :
657 "llvm.intr.vp.sext" (%A, %mask, %evl) :
664 "llvm.intr.vp.fpext" (%C, %mask, %evl) :
668 "llvm.intr.vp.fptoui" (%F, %mask, %evl) :
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/AArch64/
H A Dsve-tail-folding-forced.ll14 ; VPLANS-NEXT: EMIT vp<%2> = VF * Part + ir<0>
15 ; VPLANS-NEXT: EMIT vp<%3> = active lane mask vp<%2> <badref>
20 ; VPLANS-NEXT: EMIT vp<%4> = CANONICAL-INDUCTION
21 ; VPLANS-NEXT: ACTIVE-LANE-MASK-PHI vp<%5> = phi vp<%3>, vp<%10>
22 ; VPLANS-NEXT: vp<%6> = SCALAR-STEPS vp<%4>, ir<0>, ir<1>
24 ; VPLANS-NEXT: WIDEN store ir<%gep>, ir<%val>, vp<%5>
25 ; VPLANS-NEXT: EMIT vp<%8> = VF * UF + vp<%4>
26 ; VPLANS-NEXT: EMIT vp<%9> = VF * Part + vp<%8>
27 ; VPLANS-NEXT: EMIT vp<%10> = active lane mask vp<%9> <badref>
28 ; VPLANS-NEXT: EMIT vp<%11> = not vp<%10>
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