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/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Dmulwide.ll11 %val0 = sext i16 %a to i32
13 %val2 = mul i32 %val0, %val1
22 %val0 = zext i16 %a to i32
24 %val2 = mul i32 %val0, %val1
33 %val0 = sext i8 %a to i32
35 %val2 = mul i32 %val0, %val1
44 %val0 = zext i8 %a to i32
55 %val0 = sext i32 %a to i64
66 %val0 = zext i32 %a to i64
77 %val0 = zext i7 %a to i64
[all …]
H A Dbfe.ll10 %val0 = ashr i32 %a, 4
11 %val1 = and i32 %val0, 15
20 %val0 = ashr i32 %a, 3
21 %val1 = and i32 %val0, 7
30 %val0 = ashr i32 %a, 5
31 %val1 = and i32 %val0, 7
H A Dshift-parts.ll18 %val0 = shl i128 %a, %amt
19 store i128 %val0, i128* %val
36 %val0 = ashr i128 %a, %amt
37 store i128 %val0, i128* %val
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Damdgcn-ieee.ll11 %val0 = load volatile float, float addrspace(1)* undef
13 %min = call float @llvm.minnum.f32(float %val0, float %val1)
26 %val0 = load volatile float, float addrspace(1)* undef
41 %val0 = load volatile float, float addrspace(1)* undef
56 %val0 = load volatile float, float addrspace(1)* undef
71 %val0 = load volatile float, float addrspace(1)* undef
86 %val0 = load volatile float, float addrspace(1)* undef
101 %val0 = load volatile float, float addrspace(1)* undef
116 %val0 = load volatile float, float addrspace(1)* undef
131 %val0 = load volatile float, float addrspace(1)* undef
[all …]
H A Dds_read2_superreg.ll20 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
34 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
50 %elt0 = extractelement <4 x float> %val0, i32 0
51 %elt1 = extractelement <4 x float> %val0, i32 1
52 %elt2 = extractelement <4 x float> %val0, i32 2
53 %elt3 = extractelement <4 x float> %val0, i32 3
75 %elt0 = extractelement <3 x float> %val0, i32 0
76 %elt1 = extractelement <3 x float> %val0, i32 1
77 %elt2 = extractelement <3 x float> %val0, i32 2
161 %val0 = load float, float addrspace(3)* %arrayidx0
[all …]
H A Dcgp-bitfield-extract.ll15 ; OPT-NEXT: %val0 = and i32 %0, 255
44 %val0 = and i32 %shr, 255
65 ; OPT-NEXT: %val0 = and i32 %0, 255
84 %val0 = and i32 %shr, 255
106 ; OPT-NEXT: %val0 = and i16 %0, 255
141 %val0 = and i16 %shr, 255
166 ; OPT-NEXT: %val0 = and i64 %0, 255
192 %val0 = and i64 %shr, 255
214 ; OPT-NEXT: %val0 = and i64 %0, 255
240 %val0 = and i64 %shr, 255
[all …]
H A Dhip.extern.shared.array.ll45 %val = phi float [ %val0, %if ], [ %val1, %else ]
73 %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
74 %val1 = uitofp i8 %val0 to float
90 %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
91 %val1 = uitofp i8 %val0 to float
92 %val2 = uitofp i8 %val0 to double
110 %val1 = uitofp i8 %val0 to float
111 %val2 = uitofp i8 %val0 to double
129 %val1 = uitofp i8 %val0 to float
130 %val2 = uitofp i8 %val0 to double
[all …]
H A Dds_read2st64.ll24 %sum = fadd float %val0, %val1
47 %sum = fadd float %val0, %val1
70 %sum = fadd float %val0, %val1
93 %sum = fadd float %val0, %val1
112 %sum = fadd float %val0, %val1
132 %sum = fadd float %val0, %val1
154 %sum = fadd double %val0, %val1
178 %sum = fadd double %val0, %val1
200 %sum = fadd double %val0, %val1
225 %sum = fadd double %val0, %val1
[all …]
H A Dsminmax.v2i16.ll167 %cond0 = icmp sgt <2 x i16> %val0, %val1
168 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
169 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
180 %val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0
183 %cond0 = icmp sgt <2 x i16> %val0, %val1
184 %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
185 %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
198 %cond0 = icmp sgt <4 x i16> %val0, %val1
209 %val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0
212 %cond0 = icmp sgt <2 x i16> %val0, %val1
[all …]
H A Dsminmax.ll205 %cond0 = icmp sgt i32 %val0, %val1
206 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
207 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
221 %val0 = load volatile i32, i32 addrspace(1)* %ptr0
224 %cond0 = icmp sgt i32 %val0, %val1
225 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
226 %sel1 = select i1 %cond0, i32 %val1, i32 %val0
243 %cond0 = icmp sgt <4 x i32> %val0, %val1
261 %cond0 = icmp sgt i32 %val0, %val1
262 %sel0 = select i1 %cond0, i32 %val0, i32 %val1
[all …]
H A Dvector_shuffle.packed.ll29 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
67 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
96 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
128 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
157 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
197 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
237 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
287 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
338 %val0 = load <4 x half>, <4 x half> addrspace(1)* %arg0
1202 %val0 = load <4 x i16>, <4 x i16> addrspace(1)* %arg0
[all …]
H A Dpack.v2f16.ll12 %val0 = load volatile i32, i32 addrspace(4)* %in0
14 %lo.i = trunc i32 %val0 to i16
47 %val0 = load i32, i32 addrspace(4)* %in0
48 %lo.i = trunc i32 %val0 to i16
70 %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
72 %lo.i = trunc i32 %val0 to i16
96 %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
98 %lo.i = trunc i32 %val0 to i16
164 %lo.i = trunc i32 %val0 to i16
186 %lo.i = trunc i32 %val0 to i16
[all …]
H A Dpack.v2i16.ll12 %val0 = load volatile i32, i32 addrspace(4)* %in0
14 %lo = trunc i32 %val0 to i16
44 %val0 = load i32, i32 addrspace(4)* %in0
45 %lo = trunc i32 %val0 to i16
66 %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
68 %lo = trunc i32 %val0 to i16
90 %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
92 %lo = trunc i32 %val0 to i16
152 %val0 = load volatile i32, i32 addrspace(1)* %in0.gep
153 %lo = trunc i32 %val0 to i16
[all …]
H A Dsplit-scalar-i64-add.ll41 …@imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) {
43 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
54 define amdgpu_kernel void @s_imp_def_vcc_split_i64_add_1(i64 addrspace(1)* %out, i32 %val0, i64 %va…
55 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
67 …@imp_def_vcc_split_i64_add_2(i64 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %val0, i64 %val1) {
71 %vec.0 = insertelement <2 x i32> undef, i32 %val0, i32 0
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dhip.extern.shared.array.ll47 %val = phi float [ %val0, %if ], [ %val1, %else ]
75 %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
76 %val1 = uitofp i8 %val0 to float
91 %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
92 %val1 = uitofp i8 %val0 to float
93 %val2 = uitofp i8 %val0 to double
109 %val0 = load i8, i8 addrspace(3)* %arrayidx0, align 4
110 %val1 = uitofp i8 %val0 to float
111 %val2 = uitofp i8 %val0 to double
128 %val1 = uitofp i8 %val0 to float
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dlogical-imm.ll9 %val0 = and i32 %in32, 2863311530
10 store volatile i32 %val0, i32* @var32
31 %val0 = or i32 %in32, 2863311530
32 store volatile i32 %val0, i32* @var32
53 %val0 = xor i32 %in32, 2863311530
54 store volatile i32 %val0, i32* @var32
74 %val0 = add i32 %in32, 2863311530
75 store i32 %val0, i32* @var32
H A Ddp-3source.ll3 define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
6 %res = add i32 %val0, %mid
11 define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
14 %res = add i64 %val0, %mid
19 define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
22 %res = sub i32 %val0, %mid
27 define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
30 %res = sub i64 %val0, %mid
H A Ddag-combine-select.ll25 define void @test1(i32 %bitset, i32 %val0, i32 %val1) {
39 %cond = select i1 %cmp1, i32 %val0, i32 %val1
41 %cond11 = select i1 %cmp5, i32 %val0, i32 %val1
44 %cond17 = select i1 %or.cond, i32 %val0, i32 %val1
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmerge-consecutive-loads-256.ll60 %val0 = load double, ptr %ptr0
187 %val0 = load i64, ptr %ptr0
210 %val0 = load i64, ptr %ptr0
230 %val0 = load i64, ptr %ptr0
375 %val0 = load i32, ptr %ptr0
405 %val0 = load i32, ptr %ptr0
430 %val0 = load i16, ptr %ptr0
479 %val0 = load i16, ptr %ptr
509 %val0 = load i16, ptr %ptr
539 %val0 = load i8, ptr %ptr0
[all …]
H A Dmerge-consecutive-loads-512.ll188 %val0 = load i64, ptr %ptr0
218 %val0 = load i64, ptr %ptr0
355 %val0 = load i32, ptr %ptr0
380 %val0 = load i32, ptr %ptr0
404 %val0 = load i32, ptr %ptr
434 %val0 = load i32, ptr %ptr
464 %val0 = load i16, ptr %ptr0
489 %val0 = load i16, ptr %ptr0
511 %val0 = load i16, ptr %ptr0
538 %val0 = load i8, ptr %ptr0
[all …]
H A Dmerge-consecutive-loads-128.ll38 %val0 = load double, ptr %ptr0
87 %val0 = load i64, ptr %ptr0
114 %val0 = load float, ptr %ptr0
142 %val0 = load float, ptr %ptr0
392 %val0 = load i32, ptr %ptr0
447 %val0 = load i32, ptr %ptr0
448 %inc = add i32 %val0, 1
665 %inc = add i32 %val0, 1
932 %val0 = load i8, ptr %ptr
994 %val0 = load i8, ptr %ptr
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Daggregate-padding.ll39 %val0 = extractvalue [4 x i32] %arg, 0
41 %sum = add i32 %val0, %val3
74 %val0 = extractvalue [3 x i8] %arg, 0
76 %sum = add i8 %val0, %val2
84 %val0 = extractvalue [3 x i16] %arg, 0
86 %sum = add i16 %val0, %val2
97 %val0 = extractvalue [3 x i16] %arg, 0
99 %sum = add i16 %val0, %val2
111 %val0 = extractvalue [2 x <4 x i32>] %arg, 0
112 %val0_0 = extractelement <4 x i32> %val0, i32 0
/llvm-project-15.0.7/llvm/test/CodeGen/SystemZ/
H A Dspill-01.ll47 %val0 = load i32, i32 *%ptr0
57 store i32 %val0, i32 *%ptr0
85 %val0 = load i32, i32 *%ptr0
97 store i32 %val0, i32 *%ptr0
127 %val0 = load i64, i64 *%ptr0
139 store i64 %val0, i64 *%ptr0
186 store float %val0, float *%ptr0
327 %val0 = load i32, i32 *@g0
340 store i32 %val0, i32 *@g0
359 %val0 = load i64, i64 *@h0
[all …]
H A Dvec-combine-02.ll6 define <8 x i16> @f1(<4 x i32> %val0, <4 x i32> %val1) {
10 %elem0 = extractelement <4 x i32> %val0, i32 0
11 %elem1 = extractelement <4 x i32> %val0, i32 1
12 %elem2 = extractelement <4 x i32> %val0, i32 2
13 %elem3 = extractelement <4 x i32> %val0, i32 3
49 %elem0 = extractelement <4 x i32> %val0, i32 0
50 %elem1 = extractelement <4 x i32> %val0, i32 1
51 %elem2 = extractelement <4 x i32> %val0, i32 2
52 %elem3 = extractelement <4 x i32> %val0, i32 3
194 %elem0 = extractelement <4 x i32> %val0, i32 0
[all …]
H A Dfoldmemop-imm-01.ll18 %val0 = load i32, i32 *%src
23 %tmp0 = phi i32 [0, %entry], [%val0, %cond]
43 %val0 = load i64, i64 *%src
48 %tmp0 = phi i64 [0, %entry], [%val0, %cond]

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