Home
last modified time | relevance | path

Searched refs:v8 (Results 1 – 25 of 1470) sorted by relevance

12345678910>>...59

/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dctlz-sdnode.ll17 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
237 ; CHECK-NEXT: vnot.v v8, v8
266 ; CHECK-NEXT: vnot.v v8, v8
297 ; RV32I-NEXT: vnot.v v8, v8
330 ; RV64I-NEXT: vnot.v v8, v8
380 ; RV32I-NEXT: vnot.v v8, v8
413 ; RV64I-NEXT: vnot.v v8, v8
463 ; RV32I-NEXT: vnot.v v8, v8
496 ; RV64I-NEXT: vnot.v v8, v8
712 ; RV32-NEXT: vnot.v v8, v8
[all …]
H A Dbitreverse-sdnode.ll24 ; CHECK-NEXT: vadd.vv v8, v8, v8
51 ; CHECK-NEXT: vadd.vv v8, v8, v8
78 ; CHECK-NEXT: vadd.vv v8, v8, v8
105 ; CHECK-NEXT: vadd.vv v8, v8, v8
132 ; CHECK-NEXT: vadd.vv v8, v8, v8
159 ; CHECK-NEXT: vadd.vv v8, v8, v8
186 ; CHECK-NEXT: vadd.vv v8, v8, v8
220 ; RV32-NEXT: vadd.vv v8, v8, v8
249 ; RV64-NEXT: vadd.vv v8, v8, v8
283 ; RV32-NEXT: vadd.vv v8, v8, v8
[all …]
H A Dctpop-sdnode.ll12 ; CHECK-NEXT: vsub.vv v8, v8, v9
15 ; CHECK-NEXT: vsrl.vi v8, v8, 2
16 ; CHECK-NEXT: vand.vx v8, v8, a0
17 ; CHECK-NEXT: vadd.vv v8, v9, v8
19 ; CHECK-NEXT: vadd.vv v8, v8, v9
20 ; CHECK-NEXT: vand.vi v8, v8, 15
34 ; CHECK-NEXT: vsub.vv v8, v8, v9
37 ; CHECK-NEXT: vsrl.vi v8, v8, 2
38 ; CHECK-NEXT: vand.vx v8, v8, a0
39 ; CHECK-NEXT: vadd.vv v8, v9, v8
[all …]
H A Dcttz-sdnode.ll13 ; CHECK-ZVE64X-NEXT: vnot.v v8, v8
233 ; CHECK-NEXT: vnot.v v8, v8
259 ; CHECK-NEXT: vnot.v v8, v8
285 ; RV32I-NEXT: vnot.v v8, v8
313 ; RV64I-NEXT: vnot.v v8, v8
360 ; RV32I-NEXT: vnot.v v8, v8
388 ; RV64I-NEXT: vnot.v v8, v8
435 ; RV32I-NEXT: vnot.v v8, v8
463 ; RV64I-NEXT: vnot.v v8, v8
660 ; RV32-NEXT: vnot.v v8, v8
[all …]
H A Dfixed-vectors-ctlz.ll19 ; CHECK-NEXT: vor.vv v8, v8, v9
21 ; CHECK-NEXT: vor.vv v8, v8, v9
23 ; CHECK-NEXT: vor.vv v8, v8, v9
24 ; CHECK-NEXT: vnot.v v8, v8
28 ; CHECK-NEXT: vsub.vv v8, v8, v9
31 ; CHECK-NEXT: vsrl.vi v8, v8, 2
32 ; CHECK-NEXT: vand.vx v8, v8, a1
33 ; CHECK-NEXT: vadd.vv v8, v9, v8
35 ; CHECK-NEXT: vadd.vv v8, v8, v9
36 ; CHECK-NEXT: vand.vi v8, v8, 15
[all …]
H A Dfixed-vectors-ctpop.ll15 ; CHECK-NEXT: vsub.vv v8, v8, v9
18 ; CHECK-NEXT: vsrl.vi v8, v8, 2
19 ; CHECK-NEXT: vand.vx v8, v8, a1
20 ; CHECK-NEXT: vadd.vv v8, v9, v8
22 ; CHECK-NEXT: vadd.vv v8, v8, v9
23 ; CHECK-NEXT: vand.vi v8, v8, 15
43 ; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v9
47 ; LMULMAX2-RV32-NEXT: vsrl.vi v8, v8, 2
48 ; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
49 ; LMULMAX2-RV32-NEXT: vadd.vv v8, v9, v8
[all …]
H A Dfixed-vectors-cttz.ll20 ; CHECK-NEXT: vnot.v v8, v8
21 ; CHECK-NEXT: vand.vv v8, v8, v9
25 ; CHECK-NEXT: vsub.vv v8, v8, v9
28 ; CHECK-NEXT: vsrl.vi v8, v8, 2
29 ; CHECK-NEXT: vand.vx v8, v8, a1
30 ; CHECK-NEXT: vadd.vv v8, v9, v8
32 ; CHECK-NEXT: vadd.vv v8, v8, v9
33 ; CHECK-NEXT: vand.vi v8, v8, 15
71 ; LMULMAX2-RV32I-NEXT: vnot.v v8, v8
676 ; LMULMAX2-NEXT: vnot.v v8, v8
[all …]
H A Dfixed-vectors-bitreverse.ll34 ; RV32-NEXT: vadd.vv v8, v8, v8
65 ; RV64-NEXT: vadd.vv v8, v8, v8
113 ; RV32-NEXT: vadd.vv v8, v8, v8
153 ; RV64-NEXT: vadd.vv v8, v8, v8
244 ; RV32-NEXT: vadd.vv v8, v8, v8
303 ; RV64-NEXT: vadd.vv v8, v8, v8
342 ; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v8
373 ; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
406 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
458 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
[all …]
H A Dfixed-vectors-extract.ll283 ; CHECK-NEXT: vadd.vv v8, v8, v8
299 ; RV32-NEXT: vadd.vv v8, v8, v8
312 ; RV64-NEXT: vadd.vv v8, v8, v8
328 ; CHECK-NEXT: vfadd.vv v8, v8, v8
344 ; CHECK-NEXT: vfadd.vv v8, v8, v8
360 ; CHECK-NEXT: vfadd.vv v8, v8, v8
405 ; CHECK-NEXT: vadd.vv v8, v8, v8
421 ; RV32-NEXT: vadd.vv v8, v8, v8
434 ; RV64-NEXT: vadd.vv v8, v8, v8
502 ; RV32-NEXT: vadd.vv v8, v8, v8
[all …]
H A Dbswap-sdnode.ll10 ; CHECK-NEXT: vsll.vi v8, v8, 8
11 ; CHECK-NEXT: vor.vv v8, v8, v9
23 ; CHECK-NEXT: vsll.vi v8, v8, 8
24 ; CHECK-NEXT: vor.vv v8, v8, v9
36 ; CHECK-NEXT: vsll.vi v8, v8, 8
37 ; CHECK-NEXT: vor.vv v8, v8, v9
49 ; CHECK-NEXT: vsll.vi v8, v8, 8
50 ; CHECK-NEXT: vor.vv v8, v8, v10
62 ; CHECK-NEXT: vsll.vi v8, v8, 8
75 ; CHECK-NEXT: vsll.vi v8, v8, 8
[all …]
H A Durem-seteq-vec.ll11 ; RV32-NEXT: vmul.vx v8, v8, a0
13 ; RV32-NEXT: vsrl.vi v8, v8, 1
14 ; RV32-NEXT: vor.vv v8, v8, v9
27 ; RV64-NEXT: vmul.vx v8, v8, a0
29 ; RV64-NEXT: vsrl.vi v8, v8, 1
30 ; RV64-NEXT: vor.vv v8, v8, v9
53 ; RV32-NEXT: vmul.vx v8, v8, a0
66 ; RV64-NEXT: vmul.vx v8, v8, a0
93 ; RV32-NEXT: vsrl.vi v8, v8, 1
94 ; RV32-NEXT: vor.vv v8, v8, v9
[all …]
H A Dfixed-vectors-reduction-int.ll27 ; CHECK-NEXT: vredsum.vs v8, v8, v9
43 ; CHECK-NEXT: vredsum.vs v8, v8, v9
59 ; CHECK-NEXT: vredsum.vs v8, v8, v9
75 ; CHECK-NEXT: vredsum.vs v8, v8, v9
94 ; CHECK-NEXT: vredsum.vs v8, v8, v10
113 ; CHECK-NEXT: vredsum.vs v8, v8, v12
132 ; CHECK-NEXT: vredsum.vs v8, v8, v16
150 ; CHECK-NEXT: vadd.vv v8, v8, v16
154 ; CHECK-NEXT: vredsum.vs v8, v8, v16
212 ; CHECK-NEXT: vredsum.vs v8, v8, v9
[all …]
H A Dvslide1down-constant-vl-rv32.ll24 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
25 ; CHECK-NEXT: vslide1down.vx v8, v8, a1
48 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
49 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a1
55 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
56 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
81 ; CHECK-512-NEXT: vslide1down.vx v8, v8, a0
88 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a0
89 ; CHECK-64-NEXT: vslide1down.vx v8, v8, a1
275 ; CHECK-NEXT: vslide1down.vx v8, v8, a0
[all …]
H A Dextractelt-i1.ll12 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
14 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
30 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
32 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
48 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
50 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
66 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
68 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
84 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
86 ; CHECK-NEXT: vslidedown.vx v8, v8, a1
[all …]
H A Dvdiv-sdnode.ll11 ; CHECK-NEXT: vdiv.vv v8, v8, v9
21 ; CHECK-NEXT: vdiv.vx v8, v8, a0
35 ; CHECK-NEXT: vsub.vv v8, v9, v8
36 ; CHECK-NEXT: vsra.vi v8, v8, 2
38 ; CHECK-NEXT: vadd.vv v8, v8, v9
74 ; CHECK-NEXT: vdiv.vv v8, v8, v9
84 ; CHECK-NEXT: vdiv.vx v8, v8, a0
98 ; CHECK-NEXT: vsub.vv v8, v9, v8
99 ; CHECK-NEXT: vsra.vi v8, v8, 2
101 ; CHECK-NEXT: vadd.vv v8, v8, v9
[all …]
H A Dfixed-vectors-bswap.ll13 ; CHECK-NEXT: vsll.vi v8, v8, 8
14 ; CHECK-NEXT: vor.vv v8, v8, v9
39 ; RV32-NEXT: vsll.vi v8, v8, 24
40 ; RV32-NEXT: vor.vv v8, v8, v10
41 ; RV32-NEXT: vor.vv v8, v8, v9
58 ; RV64-NEXT: vsll.vi v8, v8, 24
59 ; RV64-NEXT: vor.vv v8, v8, v10
60 ; RV64-NEXT: vor.vv v8, v8, v9
118 ; RV32-NEXT: vsll.vx v8, v8, a1
121 ; RV32-NEXT: vor.vv v8, v8, v9
[all …]
H A Dactive_lane_mask.ll9 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
33 ; CHECK-NEXT: vsaddu.vx v8, v8, a0
45 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
84 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
96 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
110 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
113 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
129 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
132 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
140 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Darm64-verbose-vector-case.s3 pmull v8.8h, v8.8b, v8.8b
4 pmull2 v8.8h, v8.16b, v8.16b
5 pmull v8.1q, v8.1d, v8.1d
6 pmull2 v8.1q, v8.2d, v8.2d
12 pmull v8.8H, v8.8B, v8.8B
13 pmull2 v8.8H, v8.16B, v8.16B
14 pmull v8.1Q, v8.1D, v8.1D
15 pmull2 v8.1Q, v8.2D, v8.2D
H A Dneon-simd-misc.s11 rev64 v6.4s, v8.4s
44 saddlp v8.4h, v5.8b
62 uaddlp v8.4h, v5.8b
80 sadalp v8.4h, v5.8b
157 sqabs v6.4s, v8.4s
197 abs v6.4s, v8.4s
198 abs v6.2d, v8.2d
217 neg v6.4s, v8.4s
218 neg v6.2d, v8.2d
237 cls v6.4s, v8.4s
[all …]
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dds.s186 ds_add_rtn_u32 v8, v2, v4
190 ds_add_rtn_f32 v8, v2, v4
230 ds_or_rtn_b32 v8, v2, v4
278 ds_read_b32 v8, v2
290 ds_read_i8 v8, v2
294 ds_read_u8 v8, v2
298 ds_read_i16 v8, v2
302 ds_read_u16 v8, v2
307 ds_consume v8
311 ds_append v8
[all …]
H A Dds-err.s41 ds_swizzle_b32 v8, v2 offset
44 ds_swizzle_b32 v8, v2 offset:
47 ds_swizzle_b32 v8, v2 offset-
56 ds_swizzle_b32 v8, v2 offset:swizzle(XXX,1)
59 ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM
77 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,0)
80 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
83 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,17)
86 ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,32)
89 ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,1)
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/rvv/
H A Dfmacc.s20 vfmacc.vv v8, v20, v4
32 vfmacc.vf v8, fa0, v4
44 vfnmacc.vv v8, v20, v4
56 vfnmacc.vf v8, fa0, v4
68 vfmsac.vv v8, v20, v4
80 vfmsac.vf v8, fa0, v4
92 vfnmsac.vv v8, v20, v4
116 vfmadd.vv v8, v20, v4
128 vfmadd.vf v8, fa0, v4
164 vfmsub.vv v8, v20, v4
[all …]
H A Dconvert.s20 vfcvt.xu.f.v v8, v4
32 vfcvt.x.f.v v8, v4
44 vfcvt.f.xu.v v8, v4
56 vfcvt.f.x.v v8, v4
92 vfwcvt.xu.f.v v8, v4
104 vfwcvt.x.f.v v8, v4
116 vfwcvt.f.xu.v v8, v4
128 vfwcvt.f.x.v v8, v4
140 vfwcvt.f.f.v v8, v4
194 vfncvt.x.f.w v8, v4
[all …]
H A Dload.s17 vlm.v v8, (a0)
23 vle8.v v8, (a0), v0.t
29 vle8.v v8, (a0)
41 vle16.v v8, (a0)
53 vle32.v v8, (a0)
65 vle64.v v8, (a0)
77 vle8ff.v v8, (a0)
89 vle16ff.v v8, (a0)
101 vle32ff.v v8, (a0)
113 vle64ff.v v8, (a0)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dexpand-pseudos.ll9 %"class.v8::internal::Assembler" = type {}
10 %"class.v8::internal::Operand" = type { %"class.v8::internal::Register", %"class.v8::internal::Regi…
11 %"class.v8::internal::Register" = type {}
13 %"class.v8::internal::wasm::LiftoffAssembler" = type {}
19 %5 = alloca %"class.v8::internal::Operand", align 8
20 …%6 = bitcast %"class.v8::internal::wasm::LiftoffAssembler"* %0 to %"class.v8::internal::Assembler"*
22 %8 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
23 %9 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
24 %10 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
25 %11 = getelementptr %"class.v8::internal::Operand", %"class.v8::internal::Operand"* %5
[all …]

12345678910>>...59