Home
last modified time | relevance | path

Searched refs:v7 (Results 1 – 25 of 943) sorted by relevance

12345678910>>...38

/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfast-isel-ext.ll16 ; v7-LABEL: zext_1_8:
17 ; v7: and r0, r0, #1
23 ; v7-LABEL: zext_1_16:
24 ; v7: and r0, r0, #1
30 ; v7-LABEL: zext_1_32:
31 ; v7: and r0, r0, #1
52 ; v7: uxth r0, r0
60 ; v7-LABEL: sext_1_8:
85 ; v7: sxtb r0, r0
92 ; v7: sxtb r0, r0
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-compare-instructions.s12 cmeq v5.8h, v6.8h, v7.8h
14 cmeq v9.4s, v7.4s, v8.4s
34 cmhs v5.8h, v6.8h, v7.8h
36 cmhs v9.4s, v7.4s, v8.4s
42 cmls v5.8h, v7.8h, v6.8h
44 cmls v9.4s, v8.4s, v7.4s
71 cmge v5.8h, v6.8h, v7.8h
275 cmeq v9.4s, v7.4s, #0
314 cmgt v9.4s, v7.4s, #0
333 cmle v9.4s, v7.4s, #0
[all …]
H A Darm64-simd-ldst.s12 ld1.8b {v7, v8, v9, v10}, [x4]
90 st1.2d {v7, v8}, [x10]
237 ld3.2d {v7, v8, v9}, [x9]
252 st3.4s {v7, v8, v9}, [x29]
1013 ld4r.8b {v4, v5, v6, v7}, [x2]
1017 ld4r.4h {v4, v5, v6, v7}, [x2]
1019 ld4r.8h {v4, v5, v6, v7}, [x2]
1021 ld4r.2s {v4, v5, v6, v7}, [x2]
1023 ld4r.4s {v4, v5, v6, v7}, [x2]
1025 ld4r.1d {v4, v5, v6, v7}, [x2]
[all …]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Ddeprecated-v8.s14 @ CHECK-ARMV8: warning: deprecated since v7, use 'isb'
15 @ CHECK-THUMBV8: warning: deprecated since v7, use 'isb'
16 @ CHECK-ARMV7: warning: deprecated since v7, use 'isb'
17 @ CHECK-THUMBV7: warning: deprecated since v7, use 'isb'
21 @ CHECK-ARMV8: warning: deprecated since v7, use 'dsb'
22 @ CHECK-THUMBV8: warning: deprecated since v7, use 'dsb'
23 @ CHECK-ARMV7: warning: deprecated since v7, use 'dsb'
24 @ CHECK-THUMBV7: warning: deprecated since v7, use 'dsb'
28 @ CHECK-ARMV8: warning: deprecated since v7, use 'dmb'
29 @ CHECK-THUMBV8: warning: deprecated since v7, use 'dmb'
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dsdiv.i32.ll188 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6
190 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
249 ; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
253 ; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
347 ; GISEL-NEXT: v_mul_hi_u32 v7, v4, v7
396 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
537 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
702 ; CGP-NEXT: v_rcp_f32_e32 v7, v7
706 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
908 ; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
[all …]
H A Dsrem.i32.ll173 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v5
175 ; GISEL-NEXT: v_mul_hi_u32 v7, v5, v7
180 ; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7
182 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v3
228 ; CGP-NEXT: v_mul_lo_u32 v7, v7, v5
231 ; CGP-NEXT: v_mul_hi_u32 v7, v5, v7
241 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
245 ; CGP-NEXT: v_mul_lo_u32 v7, v7, v3
366 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
652 ; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
[all …]
H A Dudiv.i32.ll138 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6
140 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
181 ; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
185 ; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
324 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6
326 ; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7
369 ; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
373 ; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
491 ; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6
538 ; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
[all …]
H A Durem.i64.ll69 ; CHECK-NEXT: v_mul_lo_u32 v7, v7, v0
81 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v10, v7
91 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
113 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
1001 ; CHECK-NEXT: v_mul_hi_u32 v7, v6, v7
1024 ; CHECK-NEXT: v_mul_hi_u32 v7, v6, v7
1258 ; GISEL-NEXT: v_mul_hi_u32 v7, v3, v7
1385 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
1508 ; CGP-NEXT: v_mul_hi_u32 v7, v3, v7
1548 ; CGP-NEXT: v_mul_hi_u32 v7, s8, v7
[all …]
H A Dllvm.amdgcn.image.load.2d.ll68 ; GFX10-NEXT: v_mov_b32_e32 v7, 0
73 ; GFX10-NEXT: v_mov_b32_e32 v8, v7
74 ; GFX10-NEXT: v_mov_b32_e32 v9, v7
75 ; GFX10-NEXT: v_mov_b32_e32 v10, v7
83 ; GFX10-NEXT: v_mov_b32_e32 v0, v7
96 ; GFX11-NEXT: v_mov_b32_e32 v7, 0
101 ; GFX11-NEXT: v_mov_b32_e32 v9, v7
104 ; GFX11-NEXT: v_mov_b32_e32 v8, v7
111 ; GFX11-NEXT: v_mov_b32_e32 v0, v7
156 ; GFX10-NEXT: v_mov_b32_e32 v7, 0
[all …]
H A Dsrem.i64.ll68 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v0
117 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
482 ; GISEL-NEXT: v_trunc_f32_e32 v7, v7
485 ; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
859 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v2
908 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7
1011 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
2479 ; GISEL-NEXT: v_xor_b32_e32 v7, v8, v7
2684 ; GISEL-NEXT: v_xor_b32_e32 v7, v7, v4
3179 ; GISEL-NEXT: v_mul_hi_u32 v7, v12, v7
[all …]
/llvm-project-15.0.7/llvm/test/Analysis/CostModel/X86/
H A Dinterleaved-store-i8-stride-8.ll17 ; SSE2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i8 %v7, ptr %out7, align 1
18 ; SSE2: LV: Found an estimated cost of 56 for VF 2 For instruction: store i8 %v7, ptr %out7, align…
19 ; SSE2: LV: Found an estimated cost of 120 for VF 4 For instruction: store i8 %v7, ptr %out7, alig…
20 ; SSE2: LV: Found an estimated cost of 248 for VF 8 For instruction: store i8 %v7, ptr %out7, alig…
24 ; AVX1: LV: Found an estimated cost of 1 for VF 1 For instruction: store i8 %v7, ptr %out7, align 1
25 ; AVX1: LV: Found an estimated cost of 33 for VF 2 For instruction: store i8 %v7, ptr %out7, align…
26 ; AVX1: LV: Found an estimated cost of 67 for VF 4 For instruction: store i8 %v7, ptr %out7, align…
32 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i8 %v7, ptr %out7, align 1
33 ; AVX2: LV: Found an estimated cost of 33 for VF 2 For instruction: store i8 %v7, ptr %out7, align…
82 %v7 = add i8 %v, 7
[all …]
H A Dinterleaved-store-i16-stride-8.ll17 ; SSE2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i16 %v7, ptr %out7, align…
18 ; SSE2: LV: Found an estimated cost of 34 for VF 2 For instruction: store i16 %v7, ptr %out7, alig…
19 ; SSE2: LV: Found an estimated cost of 68 for VF 4 For instruction: store i16 %v7, ptr %out7, alig…
20 ; SSE2: LV: Found an estimated cost of 136 for VF 8 For instruction: store i16 %v7, ptr %out7, ali…
24 ; AVX1: LV: Found an estimated cost of 1 for VF 1 For instruction: store i16 %v7, ptr %out7, align…
25 ; AVX1: LV: Found an estimated cost of 35 for VF 2 For instruction: store i16 %v7, ptr %out7, alig…
26 ; AVX1: LV: Found an estimated cost of 70 for VF 4 For instruction: store i16 %v7, ptr %out7, alig…
32 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i16 %v7, ptr %out7, align…
33 ; AVX2: LV: Found an estimated cost of 35 for VF 2 For instruction: store i16 %v7, ptr %out7, alig…
84 %v7 = add i16 %v, 7
[all …]
H A Dinterleaved-store-i32-stride-8.ll16 ; SSE2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %v7, ptr %out7, align…
17 ; SSE2: LV: Found an estimated cost of 56 for VF 2 For instruction: store i32 %v7, ptr %out7, alig…
18 ; SSE2: LV: Found an estimated cost of 120 for VF 4 For instruction: store i32 %v7, ptr %out7, ali…
19 ; SSE2: LV: Found an estimated cost of 240 for VF 8 For instruction: store i32 %v7, ptr %out7, ali…
22 ; AVX1: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %v7, ptr %out7, align…
23 ; AVX1: LV: Found an estimated cost of 38 for VF 2 For instruction: store i32 %v7, ptr %out7, alig…
24 ; AVX1: LV: Found an estimated cost of 76 for VF 4 For instruction: store i32 %v7, ptr %out7, alig…
29 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i32 %v7, ptr %out7, align…
30 ; AVX2: LV: Found an estimated cost of 38 for VF 2 For instruction: store i32 %v7, ptr %out7, alig…
70 %v7 = add i32 %v, 7
[all …]
H A Dinterleaved-store-f32-stride-8.ll16 ; SSE2: LV: Found an estimated cost of 1 for VF 1 For instruction: store float %v7, ptr %out7, ali…
17 ; SSE2: LV: Found an estimated cost of 24 for VF 2 For instruction: store float %v7, ptr %out7, al…
18 ; SSE2: LV: Found an estimated cost of 56 for VF 4 For instruction: store float %v7, ptr %out7, al…
19 ; SSE2: LV: Found an estimated cost of 112 for VF 8 For instruction: store float %v7, ptr %out7, a…
22 ; AVX1: LV: Found an estimated cost of 1 for VF 1 For instruction: store float %v7, ptr %out7, ali…
23 ; AVX1: LV: Found an estimated cost of 26 for VF 2 For instruction: store float %v7, ptr %out7, al…
24 ; AVX1: LV: Found an estimated cost of 60 for VF 4 For instruction: store float %v7, ptr %out7, al…
29 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store float %v7, ptr %out7, ali…
30 ; AVX2: LV: Found an estimated cost of 26 for VF 2 For instruction: store float %v7, ptr %out7, al…
70 %v7 = fadd float %v, 7.0
[all …]
H A Dinterleaved-store-i64-stride-8.ll16 ; SSE2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %v7, ptr %out7, align…
17 ; SSE2: LV: Found an estimated cost of 56 for VF 2 For instruction: store i64 %v7, ptr %out7, alig…
18 ; SSE2: LV: Found an estimated cost of 112 for VF 4 For instruction: store i64 %v7, ptr %out7, ali…
21 ; AVX1: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %v7, ptr %out7, align…
22 ; AVX1: LV: Found an estimated cost of 44 for VF 2 For instruction: store i64 %v7, ptr %out7, alig…
23 ; AVX1: LV: Found an estimated cost of 96 for VF 4 For instruction: store i64 %v7, ptr %out7, alig…
27 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store i64 %v7, ptr %out7, align…
28 ; AVX2: LV: Found an estimated cost of 44 for VF 2 For instruction: store i64 %v7, ptr %out7, alig…
29 ; AVX2: LV: Found an estimated cost of 96 for VF 4 For instruction: store i64 %v7, ptr %out7, alig…
65 %v7 = add i64 %v, 7
[all …]
H A Dinterleaved-store-f64-stride-8.ll16 ; SSE2: LV: Found an estimated cost of 1 for VF 1 For instruction: store double %v7, ptr %out7, al…
17 ; SSE2: LV: Found an estimated cost of 24 for VF 2 For instruction: store double %v7, ptr %out7, a…
18 ; SSE2: LV: Found an estimated cost of 48 for VF 4 For instruction: store double %v7, ptr %out7, a…
21 ; AVX1: LV: Found an estimated cost of 1 for VF 1 For instruction: store double %v7, ptr %out7, al…
22 ; AVX1: LV: Found an estimated cost of 24 for VF 2 For instruction: store double %v7, ptr %out7, a…
23 ; AVX1: LV: Found an estimated cost of 56 for VF 4 For instruction: store double %v7, ptr %out7, a…
27 ; AVX2: LV: Found an estimated cost of 1 for VF 1 For instruction: store double %v7, ptr %out7, al…
28 ; AVX2: LV: Found an estimated cost of 24 for VF 2 For instruction: store double %v7, ptr %out7, a…
29 ; AVX2: LV: Found an estimated cost of 56 for VF 4 For instruction: store double %v7, ptr %out7, a…
65 %v7 = fadd double %v, 7.0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/
H A Dhwloop-ne.ll22 %v7 = add nsw i32 %v1, 1
23 %v8 = icmp ne i32 %v7, %a2
49 %v7 = add nsw i32 %v1, 2
50 %v8 = icmp ne i32 %v7, %a2
76 %v7 = add nsw i32 %v1, 4
77 %v8 = icmp ne i32 %v7, %a2
103 %v7 = add nsw i32 %v1, 8
130 %v7 = add nsw i32 %v1, 16
157 %v7 = add nsw i32 %v1, 1
184 %v7 = add nsw i32 %v1, 2
[all …]
H A Dhwloop-le.ll22 %v7 = add nsw i32 %v1, 1
23 %v8 = icmp sle i32 %v7, %a2
49 %v7 = add nsw i32 %v1, 2
50 %v8 = icmp sle i32 %v7, %a2
76 %v7 = add nsw i32 %v1, 4
103 %v7 = add nsw i32 %v1, 8
130 %v7 = add nsw i32 %v1, 16
157 %v7 = add nsw i32 %v1, 1
184 %v7 = add nsw i32 %v1, 2
211 %v7 = add nsw i32 %v1, 4
[all …]
H A Dmul64-sext.ll13 %v7 = mul nsw i64 %v6, %v4
14 ret i64 %v7
27 %v7 = mul nsw i64 %v6, %v4
28 ret i64 %v7
41 %v7 = mul nsw i64 %v6, %v4
42 ret i64 %v7
55 %v7 = mul nsw i64 %v3, %v6
56 ret i64 %v7
69 %v8 = mul nsw i64 %v7, %v5
84 %v7 = sext i32 %v6 to i64
[all …]
H A DPR33749.ll18 %v7 = phi i32 [ %v29, %b28 ], [ %v5, %b1 ]
19 %v8 = mul nsw i32 %v4, %v7
20 %v9 = add nsw i32 %v8, %v7
21 %v10 = mul i32 %v7, %v7
24 %v13 = mul nsw i32 %v12, %v7
25 %v14 = add nsw i32 %v13, %v7
29 %v18 = mul i32 %v10, %v7
35 %v24 = sub nsw i32 %v7, %v23
37 %v26 = sub i32 0, %v7
42 %v29 = add nsw i32 %v3, %v7
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dfrem.ll1012 ; SI-NEXT: v_not_b32_e32 v7, v7
1219 ; SI-NEXT: v_not_b32_e32 v7, v7
1407 ; SI-NEXT: v_not_b32_e32 v7, v7
1918 ; SI-NEXT: v_fma_f32 v7, v8, v7, v7
2021 ; CI-NEXT: v_fma_f32 v7, v8, v7, v7
2435 ; VI-NEXT: v_fma_f32 v7, v8, v7, v7
2462 ; GFX9-NEXT: v_fma_f32 v7, v8, v7, v7
2668 ; SI-NEXT: v_fma_f32 v7, v8, v7, v7
2749 ; CI-NEXT: v_fma_f32 v7, v8, v7, v7
2828 ; VI-NEXT: v_fma_f32 v7, v10, v7, v7
[all …]
H A Dbypass-div.ll38 ; GFX9-NEXT: v_mul_lo_u32 v5, v7, v12
77 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v0
185 ; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7
202 ; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7
364 ; GFX9-NEXT: v_add_co_u32_e32 v7, vcc, v7, v0
388 ; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, v8, s[6:7]
468 ; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7
485 ; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7
826 ; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v1, v7, vcc
898 ; GFX9-NEXT: v_add3_u32 v7, v5, v6, v7
[all …]
/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx11_asm_mimg_err.s27 image_sample_d_o v[64:66], [v32, v16, v0, v2, v4, v5, v6, v7, v8, v9], s[4:11], s[100:103] dmask:0x…
54 image_gather4_c_b_cl v[64:67], [v32, v0, v4, v5, v6, v7], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC…
66 image_gather4_b_cl_o v[64:67], [v32, v0, v4, v5, v6, v7], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC…
72 image_gather4_c_cl_o v[64:67], [v32, v0, v4, v5, v6, v7], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC…
75 image_gather4_c_l_o v[64:67], [v32, v0, v4, v5, v6, v7], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_…
78 image_gather4_c_b_o v[64:67], [v32, v0, v4, v5, v6, v7], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_…
81 image_gather4_c_b_cl_o v[64:67], [v32, v0, v4, v5, v6, v7, v8], s[4:11], s[100:103] dmask:0x1 dim:S…
84 image_sample_cd v[64:66], [v32, v16, v0, v2, v1, v4, v5, v6, v7], s[4:11], s[100:103] dmask:0x7 dim…
87 image_sample_cd_cl v[64:66], [v32, v16, v0, v2, v1, v4, v5, v6, v7, v8], s[4:11], s[100:103] dmask:…
90 image_sample_c_cd v[64:66], [v32, v16, v0, v2, v1, v4, v5, v6, v7, v8], s[4:11], s[100:103] dmask:0…
[all …]
/llvm-project-15.0.7/llvm/test/MC/Hexagon/
H A Dv60-alu.s57 v22.ub=vsub(v24.ub,v7.ub):sat
69 v11.w=vadd(v7.w,v13.w):sat
72 v4.b=vsub(v7.b,v8.b)
84 v4.uw=vabsdiff(v5.w,v7.w)
93 v7.ub=vavg(v25.ub,v28.ub)
138 v7.w=vadd(v23.w,v25.w)
149 #CHECK: 1c5ac767 { v7.h = vadd(v7.h,{{ *}}v26.h):sat }
150 v7.h=vadd(v7.h,v26.h):sat
231 v14.b=vshuffe(v7.b,v31.b)
267 if (!q1) v9.h+=v7.h
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dvintrp.txt3 #VI: v_interp_p1_f32_e32 v7, v212, attr16.y
6 #VI: v_interp_p2_f32_e32 v7, v212, attr16.y
9 #VI: v_interp_mov_f32_e32 v7, invalid_param_212, attr16.y
12 #VI: v_interp_mov_f32_e32 v7, p10, attr16.y
15 #VI: v_interp_mov_f32_e32 v7, p20, attr16.y
18 #VI: v_interp_mov_f32_e32 v7, p0, attr16.y
21 #VI: v_interp_mov_f32_e32 v7, invalid_param_3, attr16.y

12345678910>>...38