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/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dvopc-vi.s5 v_cmp_class_f16 vcc, v2, v4
9 v_cmpx_class_f16 vcc, v2, v4
13 v_cmp_f_f16 vcc, v2, v4
17 v_cmp_lt_f16 vcc, v2, v4
21 v_cmp_eq_f16 vcc, v2, v4
25 v_cmp_le_f16 vcc, v2, v4
29 v_cmp_gt_f16 vcc, v2, v4
33 v_cmp_lg_f16 vcc, v2, v4
37 v_cmp_ge_f16 vcc, v2, v4
41 v_cmp_o_f16 vcc, v2, v4
[all …]
H A Dflat-scratch-gfx940.s3 scratch_load_dword a2, v4, s6
6 scratch_load_dword a2, v4, s6 offset:16
9 scratch_load_dword a2, v4, off
27 scratch_load_dword v2, v4, s6
33 scratch_load_dword v2, v4, off
195 scratch_load_sbyte a2, v4, s6
201 scratch_load_sbyte a2, v4, off
219 scratch_load_sbyte v2, v4, s6
225 scratch_load_sbyte v2, v4, off
483 scratch_load_ubyte a2, v4, s6
[all …]
H A Dds.s66 ds_add_u32 v2, v4
70 ds_add_f32 v2, v4
74 ds_sub_u32 v2, v4
82 ds_inc_u32 v2, v4
86 ds_dec_u32 v2, v4
90 ds_min_i32 v2, v4
94 ds_max_i32 v2, v4
98 ds_min_u32 v2, v4
102 ds_max_u32 v2, v4
106 ds_and_b32 v2, v4
[all …]
H A Dgfx11_mtbuf_alias.s4 tbuffer_load_format_d16_x v4, off, s[8:11], s3, format:[BUF_FMT_8_UNORM] offset:4095
16 tbuffer_load_format_d16_x v4, off, s[12:15], m0, format:2 offset:4095
25 tbuffer_load_format_d16_x v4, off, ttmp[4:7], 61, format:3 offset:4095
43 tbuffer_load_format_d16_x v4, off, ttmp[4:7], s3, format:5 offset:4095 dlc
61 tbuffer_load_format_d16_xy v4, off, s[12:15], m0, format:7 offset:4095
70 tbuffer_load_format_d16_xy v4, off, ttmp[4:7], 61, format:8 offset:4095
88 tbuffer_load_format_d16_xy v4, off, ttmp[4:7], s3, format:10 offset:4095 dlc
196 tbuffer_store_format_d16_x v4, off, s[12:15], m0, format:42 offset:4095
205 tbuffer_store_format_d16_x v4, off, ttmp[4:7], 61, format:43 offset:4095
241 tbuffer_store_format_d16_xy v4, off, s[12:15], m0, format:47 offset:4095
[all …]
H A Dgfx11_asm_mimg_err.s3 image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_…
9 image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1, v5], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_…
33 image_sample_b_cl_o v[64:66], [v32, v16, v0, v2, v1, v4], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC…
45 image_sample_c_l_o v[64:66], [v32, v16, v0, v2, v1, v4], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_…
48 image_sample_c_b_o v[64:66], [v32, v16, v0, v2, v1, v4], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_…
57 image_gather4_cl_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D
60 image_gather4_l_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D
63 image_gather4_b_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D
69 image_gather4_c_o v[64:67], [v32, v0, v4, v5, v6], s[4:11], s[100:103] dmask:0x1 dim:SQ_RSRC_IMG_3D
111 image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
[all …]
H A Dgfx11_mtbuf.s16 tbuffer_load_d16_format_x v4, off, s[12:15], m0, format:2 offset:4095
25 tbuffer_load_d16_format_x v4, off, ttmp[4:7], 61, format:3 offset:4095
43 tbuffer_load_d16_format_x v4, off, ttmp[4:7], s3, format:5 offset:4095 dlc
61 tbuffer_load_d16_format_xy v4, off, s[12:15], m0, format:7 offset:4095
70 tbuffer_load_d16_format_xy v4, off, ttmp[4:7], 61, format:8 offset:4095
196 tbuffer_load_format_x v4, off, s[12:15], m0, format:22 offset:4095
205 tbuffer_load_format_x v4, off, ttmp[4:7], 61, format:23 offset:4095
223 tbuffer_load_format_x v4, off, ttmp[4:7], s3, format:25 offset:4095 dlc
376 tbuffer_store_d16_format_x v4, off, s[12:15], m0, format:42 offset:4095
556 tbuffer_store_format_x v4, off, s[12:15], m0, format:62 offset:4095
[all …]
/llvm-project-15.0.7/llvm/test/MC/RISCV/rvv/
H A Dfmacc.s20 vfmacc.vv v8, v20, v4
32 vfmacc.vf v8, fa0, v4
44 vfnmacc.vv v8, v20, v4
56 vfnmacc.vf v8, fa0, v4
68 vfmsac.vv v8, v20, v4
80 vfmsac.vf v8, fa0, v4
92 vfnmsac.vv v8, v20, v4
116 vfmadd.vv v8, v20, v4
128 vfmadd.vf v8, fa0, v4
164 vfmsub.vv v8, v20, v4
[all …]
H A Dconvert.s20 vfcvt.xu.f.v v8, v4
32 vfcvt.x.f.v v8, v4
44 vfcvt.f.xu.v v8, v4
56 vfcvt.f.x.v v8, v4
92 vfwcvt.xu.f.v v8, v4
104 vfwcvt.x.f.v v8, v4
128 vfwcvt.f.x.v v8, v4
140 vfwcvt.f.f.v v8, v4
176 vfncvt.xu.f.w v4, v4, v0.t
177 # CHECK-INST: vfncvt.xu.f.w v4, v4, v0.t
[all …]
H A Dadd.s17 vadd.vv v8, v4, v20
29 vadd.vx v8, v4, a0
41 vadd.vi v8, v4, 15
65 vwaddu.vx v8, v4, a0
77 vwadd.vv v8, v4, v20
89 vwadd.vx v8, v4, a0
137 vwadd.wx v8, v4, a0
149 vadc.vvm v4, v4, v20, v0
150 # CHECK-INST: vadc.vvm v4, v4, v20, v0
179 vmadc.vvm v4, v4, v20, v0
[all …]
H A Dfcompare.s20 vmfeq.vv v8, v4, v20
32 vmfeq.vf v8, v4, fa0
44 vmfne.vv v8, v4, v20
56 vmfne.vf v8, v4, fa0
68 vmflt.vv v8, v4, v20
80 vmflt.vf v8, v4, fa0
92 vmfle.vv v8, v4, v20
104 vmfle.vf v8, v4, fa0
116 vmfgt.vf v8, v4, fa0
128 vmfge.vf v8, v4, fa0
[all …]
H A Dcompare.s23 vmseq.vv v8, v4, v20
35 vmseq.vx v8, v4, a0
47 vmseq.vi v8, v4, 15
59 vmsne.vv v8, v4, v20
71 vmsne.vx v8, v4, a0
83 vmsne.vi v8, v4, 15
131 vmslt.vx v8, v4, a0
318 # CHECK-INST: vmsne.vv v8, v4, v4, v0.t
324 # CHECK-INST: vmsne.vv v8, v4, v4
354 # CHECK-INST: vmseq.vv v8, v4, v4, v0.t
[all …]
H A Dsub.s17 vsub.vv v8, v4, v20
29 vsub.vx v8, v4, a0
41 vrsub.vx v8, v4, a0
53 vrsub.vi v8, v4, 15
77 vwsubu.vx v8, v4, a0
101 vwsub.vx v8, v4, a0
149 vwsub.wx v8, v4, a0
161 vsbc.vvm v4, v4, v20, v0
162 # CHECK-INST: vsbc.vvm v4, v4, v20, v0
185 vmsbc.vvm v4, v4, v20, v0
[all …]
H A Dshift.s17 vsll.vv v8, v4, v20
29 vsll.vx v8, v4, a0
41 vsll.vi v8, v4, 31
53 vsrl.vv v8, v4, v20
65 vsrl.vx v8, v4, a0
77 vsrl.vi v8, v4, 31
89 vsra.vv v8, v4, v20
101 vsra.vx v8, v4, a0
113 vsra.vi v8, v4, 31
125 vnsrl.wv v4, v4, v20, v0.t
[all …]
H A Dmacc.s11 vmacc.vv v8, v20, v4, v0.t
17 vmacc.vv v8, v20, v4
29 vmacc.vx v8, a0, v4
41 vnmsac.vv v8, v20, v4
53 vnmsac.vx v8, a0, v4
65 vmadd.vv v8, v20, v4
77 vmadd.vx v8, a0, v4
89 vnmsub.vv v8, v20, v4
101 vnmsub.vx v8, a0, v4
125 vwmaccu.vx v8, a0, v4
[all …]
H A Dmul.s11 vmul.vv v8, v4, v20, v0.t
17 vmul.vv v8, v4, v20
29 vmul.vx v8, v4, a0
41 vmulh.vv v8, v4, v20
53 vmulh.vx v8, v4, a0
65 vmulhu.vv v8, v4, v20
77 vmulhu.vx v8, v4, a0
113 vwmul.vv v8, v4, v20
125 vwmul.vx v8, v4, a0
149 vwmulu.vx v8, v4, a0
[all …]
H A Dothers.s11 vmerge.vvm v8, v4, v20, v0
17 vmerge.vxm v8, v4, a0, v0
23 vmerge.vim v8, v4, 15, v0
35 vslideup.vx v8, v4, a0
47 vslideup.vi v8, v4, 31
59 vslidedown.vx v8, v4, a0
71 vslidedown.vi v8, v4, 31
83 vslide1up.vx v8, v4, a0
107 vrgather.vv v8, v4, v20
119 vrgather.vx v8, v4, a0
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dneon-simd-misc.s10 rev64 v2.8h, v4.8h
14 rev64 v4.2s, v0.2s
24 rev32 v4.8h, v7.8h
196 abs v2.8h, v4.8h
201 abs v4.2s, v0.2s
216 neg v2.8h, v4.8h
221 neg v4.2s, v0.2s
236 cls v2.8h, v4.8h
240 cls v4.2s, v0.2s
254 clz v2.8h, v4.8h
[all …]
H A Darm64-simd-ldst.s10 ld1.8b {v3, v4}, [x2]
11 ld1.8b {v4, v5, v6}, [x3]
851 ld1r.8b {v4}, [x2]
853 ld1r.16b {v4}, [x2]
855 ld1r.4h {v4}, [x2]
857 ld1r.8h {v4}, [x2]
859 ld1r.2s {v4}, [x2]
861 ld1r.4s {v4}, [x2]
863 ld1r.1d {v4}, [x2]
865 ld1r.2d {v4}, [x2]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dsdiv.i32.ll19 ; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4
21 ; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4
24 ; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
25 ; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4
242 ; CGP-NEXT: v_rcp_f32_e32 v4, v4
246 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
259 ; CGP-NEXT: v_mul_hi_u32 v4, v0, v4
398 ; CGP-NEXT: v_mul_lo_u32 v4, v4, v7
400 ; CGP-NEXT: v_mul_hi_u32 v4, v7, v4
404 ; CGP-NEXT: v_mul_hi_u32 v4, v1, v4
[all …]
H A Dfdiv.f32.ll59 ; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
76 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
236 ; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
325 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4
775 ; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
1347 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
1377 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
1423 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
1608 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
1638 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvv-intrinsics/
H A Dvluxseg_mf.c71 return vluxseg5ei8_v_i8mf8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei8_v_i8mf8()
92 return vluxseg6ei8_v_i8mf8(v0, v1, v2, v3, v4, v5, base, bindex, vl); in test_vluxseg6ei8_v_i8mf8()
204 return vluxseg5ei8_v_i8mf4(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei8_v_i8mf4()
337 return vluxseg5ei8_v_i8mf2(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei8_v_i8mf2()
470 return vluxseg5ei16_v_i8mf8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei16_v_i8mf8()
603 return vluxseg5ei16_v_i8mf4(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei16_v_i8mf4()
736 return vluxseg5ei16_v_i8mf2(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei16_v_i8mf2()
869 return vluxseg5ei32_v_i8mf8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei32_v_i8mf8()
1002 return vluxseg5ei32_v_i8mf4(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei32_v_i8mf4()
1135 return vluxseg5ei32_v_i8mf2(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei32_v_i8mf2()
[all …]
H A Dvloxseg_mf.c71 return vloxseg5ei8_v_i8mf8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei8_v_i8mf8()
92 return vloxseg6ei8_v_i8mf8(v0, v1, v2, v3, v4, v5, base, bindex, vl); in test_vloxseg6ei8_v_i8mf8()
204 return vloxseg5ei8_v_i8mf4(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei8_v_i8mf4()
337 return vloxseg5ei8_v_i8mf2(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei8_v_i8mf2()
470 return vloxseg5ei16_v_i8mf8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei16_v_i8mf8()
603 return vloxseg5ei16_v_i8mf4(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei16_v_i8mf4()
736 return vloxseg5ei16_v_i8mf2(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei16_v_i8mf2()
869 return vloxseg5ei32_v_i8mf8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei32_v_i8mf8()
1002 return vloxseg5ei32_v_i8mf4(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei32_v_i8mf4()
1135 return vloxseg5ei32_v_i8mf2(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei32_v_i8mf2()
[all …]
H A Dvlseg.c125 return vlseg5e8_v_i8mf8(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e8_v_i8mf8()
163 return vlseg6e8_v_i8mf8(v0, v1, v2, v3, v4, v5, base, vl); in test_vlseg6e8_v_i8mf8()
363 return vlseg5e8_v_i8mf4(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e8_v_i8mf4()
601 return vlseg5e8_v_i8mf2(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e8_v_i8mf2()
839 return vlseg5e8_v_i8m1(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e8_v_i8m1()
1653 return vlseg5e16_v_i16m1(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e16_v_i16m1()
2229 return vlseg5e32_v_i32m1(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e32_v_i32m1()
2905 return vlseg5e8_v_u8mf8(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e8_v_u8mf8()
3143 return vlseg5e8_v_u8mf4(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e8_v_u8mf4()
3381 return vlseg5e8_v_u8mf2(v0, v1, v2, v3, v4, base, vl); in test_vlseg5e8_v_u8mf2()
[all …]
/llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/
H A Dvloxseg_mf.c71 return vloxseg5ei8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei8_v_i8mf8()
92 return vloxseg6ei8(v0, v1, v2, v3, v4, v5, base, bindex, vl); in test_vloxseg6ei8_v_i8mf8()
204 return vloxseg5ei8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei8_v_i8mf4()
337 return vloxseg5ei8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei8_v_i8mf2()
470 return vloxseg5ei16(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei16_v_i8mf8()
603 return vloxseg5ei16(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei16_v_i8mf4()
736 return vloxseg5ei16(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei16_v_i8mf2()
869 return vloxseg5ei32(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei32_v_i8mf8()
1002 return vloxseg5ei32(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei32_v_i8mf4()
1667 return vloxseg5ei8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vloxseg5ei8_v_i16mf4()
[all …]
H A Dvluxseg_mf.c71 return vluxseg5ei8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei8_v_i8mf8()
92 return vluxseg6ei8(v0, v1, v2, v3, v4, v5, base, bindex, vl); in test_vluxseg6ei8_v_i8mf8()
204 return vluxseg5ei8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei8_v_i8mf4()
337 return vluxseg5ei8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei8_v_i8mf2()
470 return vluxseg5ei16(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei16_v_i8mf8()
603 return vluxseg5ei16(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei16_v_i8mf4()
736 return vluxseg5ei16(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei16_v_i8mf2()
869 return vluxseg5ei32(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei32_v_i8mf8()
1002 return vluxseg5ei32(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei32_v_i8mf4()
1667 return vluxseg5ei8(v0, v1, v2, v3, v4, base, bindex, vl); in test_vluxseg5ei8_v_i16mf4()
[all …]

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