Lines Matching refs:v4
23 ; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
26 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
27 ; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
29 ; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
39 ; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
43 ; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
44 ; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
46 ; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
57 ; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
58 ; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
59 ; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
60 ; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
62 ; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
64 ; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
73 ; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
75 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
76 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
77 ; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
79 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
82 ; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
93 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
94 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
95 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3
96 ; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5
97 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3
98 ; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5
99 ; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
108 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
113 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
114 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
116 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
131 ; GFX11-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
132 ; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
134 ; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3
135 ; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5
137 ; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3
138 ; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5
140 ; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
149 ; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
157 ; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
158 ; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
161 ; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
205 ; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
208 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
209 ; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
211 ; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
234 ; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
235 ; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
236 ; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
237 ; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
239 ; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
241 ; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
252 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
253 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
254 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3
255 ; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5
256 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3
257 ; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5
258 ; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
283 ; GFX11-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
284 ; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
286 ; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3
287 ; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5
289 ; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3
290 ; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5
292 ; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
321 ; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
322 ; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2
323 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
324 ; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
325 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4
326 ; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
327 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
338 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
339 ; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v2
340 ; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
341 ; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
342 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v4
343 ; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
345 ; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
355 ; GFX89-IEEE-NEXT: v_fma_f32 v4, -v1, v3, 1.0
356 ; GFX89-IEEE-NEXT: v_fma_f32 v3, v4, v3, v3
357 ; GFX89-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
358 ; GFX89-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v2
359 ; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v3, v4
360 ; GFX89-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v2
361 ; GFX89-IEEE-NEXT: v_div_fmas_f32 v1, v1, v3, v4
372 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v1, v3, 1.0
373 ; GFX89-FLUSH-NEXT: v_fma_f32 v3, v4, v3, v3
374 ; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v3
375 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v2
376 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v3, v4
377 ; GFX89-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v2
379 ; GFX89-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v3, v4
388 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
392 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2
393 ; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4
395 ; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4
408 ; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
409 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
410 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
411 ; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
412 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
413 ; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
415 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
424 ; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
431 ; GFX11-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2
432 ; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4
435 ; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4
451 ; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
452 ; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
454 ; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
455 ; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
457 ; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
458 ; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
461 ; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
475 ; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
476 ; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2
477 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
478 ; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
479 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4
480 ; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
481 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
492 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
493 ; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v2
494 ; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
495 ; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
496 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v4
497 ; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
499 ; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
509 ; GFX89-IEEE-NEXT: v_fma_f32 v4, -v1, v3, 1.0
510 ; GFX89-IEEE-NEXT: v_fma_f32 v3, v4, v3, v3
511 ; GFX89-IEEE-NEXT: v_mul_f32_e32 v4, v2, v3
512 ; GFX89-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v2
513 ; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v3, v4
514 ; GFX89-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v2
515 ; GFX89-IEEE-NEXT: v_div_fmas_f32 v1, v1, v3, v4
526 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v1, v3, 1.0
527 ; GFX89-FLUSH-NEXT: v_fma_f32 v3, v4, v3, v3
528 ; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v3
529 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v2
530 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v3, v4
531 ; GFX89-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v2
533 ; GFX89-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v3, v4
542 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
546 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2
547 ; GFX10-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4
549 ; GFX10-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4
562 ; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
563 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
564 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
565 ; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
566 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
567 ; GFX10-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
569 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
578 ; GFX11-IEEE-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
585 ; GFX11-IEEE-NEXT: v_mul_f32_e32 v3, v4, v2
586 ; GFX11-IEEE-NEXT: v_fma_f32 v5, -v1, v3, v4
589 ; GFX11-IEEE-NEXT: v_fma_f32 v1, -v1, v3, v4
605 ; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
606 ; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v2, v4, v2
608 ; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
609 ; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
611 ; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v5, v2
612 ; GFX11-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
615 ; GFX11-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
744 ; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
747 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
748 ; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
750 ; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
773 ; GFX89-IEEE-NEXT: v_rcp_f32_e32 v4, v2
774 ; GFX89-IEEE-NEXT: v_fma_f32 v5, -v2, v4, 1.0
775 ; GFX89-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
776 ; GFX89-IEEE-NEXT: v_mul_f32_e32 v5, v3, v4
778 ; GFX89-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
780 ; GFX89-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
791 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
792 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
793 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3
794 ; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5
795 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3
796 ; GFX10-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5
797 ; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
822 ; GFX11-IEEE-NEXT: v_fma_f32 v4, -v2, v3, 1.0
823 ; GFX11-IEEE-NEXT: v_fmac_f32_e32 v3, v4, v3
825 ; GFX11-IEEE-NEXT: v_mul_f32_e32 v4, v5, v3
826 ; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, v5
828 ; GFX11-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v3
829 ; GFX11-IEEE-NEXT: v_fma_f32 v2, -v2, v4, v5
831 ; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v4
857 ; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
858 ; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
860 ; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
863 ; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
865 ; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
866 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
869 ; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
871 ; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
872 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
873 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4
875 ; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
877 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6
884 ; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
885 ; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
888 ; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
891 ; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
893 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
895 ; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
898 ; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
901 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v5, v6, 1.0
902 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, v4, v6, v6
903 ; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v2, v4
905 ; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6
908 ; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6
915 ; GFX89-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
919 ; GFX89-IEEE-NEXT: v_rcp_f32_e32 v8, v4
921 ; GFX89-IEEE-NEXT: v_fma_f32 v10, -v4, v8, 1.0
927 ; GFX89-IEEE-NEXT: v_fma_f32 v12, -v4, v10, v6
931 ; GFX89-IEEE-NEXT: v_fma_f32 v4, -v4, v10, v6
933 ; GFX89-IEEE-NEXT: v_div_fmas_f32 v4, v4, v8, v10
936 ; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
943 ; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
945 ; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v6, v4
947 ; GFX89-FLUSH-NEXT: v_fma_f32 v7, -v4, v6, 1.0
950 ; GFX89-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v5
952 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v5
955 ; GFX89-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v6, v7
958 ; GFX89-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
962 ; GFX89-FLUSH-NEXT: v_mul_f32_e32 v4, v6, v2
963 ; GFX89-FLUSH-NEXT: v_fma_f32 v7, -v5, v4, v6
964 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, v7, v2, v4
965 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v5, v4, v6
967 ; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v5, v2, v4
975 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
978 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v4
980 ; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
987 ; GFX10-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
991 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
993 ; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
996 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
1004 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
1006 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
1008 ; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
1011 ; GFX10-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
1013 ; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
1016 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
1018 ; GFX10-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
1021 ; GFX10-FLUSH-NEXT: v_fma_f32 v4, -v6, v5, 1.0
1022 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v5, v4, v5
1023 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v5
1024 ; GFX10-FLUSH-NEXT: v_fma_f32 v7, -v6, v4, v2
1025 ; GFX10-FLUSH-NEXT: v_fmac_f32_e32 v4, v7, v5
1026 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v6, v4, v2
1028 ; GFX10-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v5, v4
1036 ; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
1040 ; GFX11-IEEE-NEXT: v_rcp_f32_e32 v6, v4
1043 ; GFX11-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
1051 ; GFX11-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
1057 ; GFX11-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
1060 ; GFX11-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
1064 ; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
1073 ; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
1076 ; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
1079 ; GFX11-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
1083 ; GFX11-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
1086 ; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
1090 ; GFX11-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
1093 ; GFX11-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
1097 ; GFX11-FLUSH-NEXT: v_fma_f32 v4, -v6, v5, 1.0
1098 ; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v5, v4, v5
1100 ; GFX11-FLUSH-NEXT: v_mul_f32_e32 v4, v2, v5
1101 ; GFX11-FLUSH-NEXT: v_fma_f32 v7, -v6, v4, v2
1103 ; GFX11-FLUSH-NEXT: v_fmac_f32_e32 v4, v7, v5
1104 ; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v6, v4, v2
1107 ; GFX11-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v5, v4
1151 ; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
1152 ; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
1154 ; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
1157 ; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
1159 ; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
1160 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
1163 ; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
1165 ; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
1166 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
1167 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4
1169 ; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
1171 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6
1179 ; GCN-FLUSH-NEXT: v_mov_b32_e32 v4, 0x2f800000
1181 ; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
1183 ; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc
1185 ; GCN-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v4
1191 ; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v1
1197 ; GFX89-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
1201 ; GFX89-IEEE-NEXT: v_rcp_f32_e32 v8, v4
1203 ; GFX89-IEEE-NEXT: v_fma_f32 v10, -v4, v8, 1.0
1209 ; GFX89-IEEE-NEXT: v_fma_f32 v12, -v4, v10, v6
1213 ; GFX89-IEEE-NEXT: v_fma_f32 v4, -v4, v10, v6
1215 ; GFX89-IEEE-NEXT: v_div_fmas_f32 v4, v4, v8, v10
1218 ; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
1226 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
1229 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v4
1231 ; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
1238 ; GFX10-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
1242 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
1244 ; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
1247 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
1256 ; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
1258 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
1264 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0
1273 ; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
1277 ; GFX11-IEEE-NEXT: v_rcp_f32_e32 v6, v4
1280 ; GFX11-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
1288 ; GFX11-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
1294 ; GFX11-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
1297 ; GFX11-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
1301 ; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
1312 ; GFX11-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s0
1316 ; GFX11-FLUSH-NEXT: v_dual_mul_f32 v2, v2, v4 :: v_dual_mul_f32 v3, v3, v5
1322 ; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1
1334 ; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1337 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
1338 ; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
1340 ; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
1343 ; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
1346 ; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
1347 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
1348 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
1350 ; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
1352 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
1361 ; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1365 ; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
1366 ; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
1368 ; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
1372 ; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
1376 ; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
1377 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
1378 ; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
1380 ; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
1383 ; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
1392 ; GFX89-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1400 ; GFX89-IEEE-NEXT: v_mul_f32_e32 v8, v4, v6
1402 ; GFX89-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v4
1406 ; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v4
1420 ; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
1422 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
1423 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
1424 ; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
1426 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
1430 ; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
1431 ; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
1437 ; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v2
1438 ; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v4
1440 ; GFX89-FLUSH-NEXT: v_fma_f32 v3, -v3, v5, v4
1453 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2
1455 ; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
1457 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v4
1460 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
1464 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
1468 ; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
1480 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1485 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
1486 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
1488 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
1490 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v1, v1, 1.0
1492 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v4
1496 ; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
1499 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2
1501 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2
1515 ; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v2
1518 ; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
1521 ; GFX11-IEEE-NEXT: v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v5
1523 ; GFX11-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
1529 ; GFX11-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
1535 ; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
1549 ; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1557 ; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
1558 ; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
1561 ; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
1563 ; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
1566 ; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v4
1572 ; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
1576 ; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2
1579 ; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2
1595 ; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1598 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
1599 ; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
1601 ; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
1604 ; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
1607 ; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
1608 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
1609 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
1611 ; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
1613 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
1622 ; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1626 ; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
1627 ; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
1629 ; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
1633 ; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
1637 ; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
1638 ; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
1639 ; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
1641 ; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
1644 ; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
1653 ; GFX89-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
1661 ; GFX89-IEEE-NEXT: v_mul_f32_e32 v8, v4, v6
1663 ; GFX89-IEEE-NEXT: v_fma_f32 v10, -v2, v8, v4
1667 ; GFX89-IEEE-NEXT: v_fma_f32 v2, -v2, v8, v4
1681 ; GFX89-FLUSH-NEXT: v_rcp_f32_e32 v4, v2
1683 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, -v2, v4, 1.0
1684 ; GFX89-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
1685 ; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v3, v4
1687 ; GFX89-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
1691 ; GFX89-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
1692 ; GFX89-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
1698 ; GFX89-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v2
1699 ; GFX89-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v4
1701 ; GFX89-FLUSH-NEXT: v_fma_f32 v3, -v3, v5, v4
1714 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v4, v2
1716 ; GFX10-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
1718 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v4, v6, v4
1721 ; GFX10-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
1725 ; GFX10-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
1729 ; GFX10-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
1741 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1746 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
1747 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
1749 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
1751 ; GFX10-FLUSH-NEXT: v_div_scale_f32 v4, s4, v1, v1, 1.0
1753 ; GFX10-FLUSH-NEXT: v_rcp_f32_e32 v3, v4
1757 ; GFX10-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
1760 ; GFX10-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2
1762 ; GFX10-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2
1776 ; GFX11-IEEE-NEXT: v_rcp_f32_e32 v4, v2
1779 ; GFX11-IEEE-NEXT: v_fma_f32 v6, -v2, v4, 1.0
1782 ; GFX11-IEEE-NEXT: v_dual_fmac_f32 v4, v6, v4 :: v_dual_fmac_f32 v5, v7, v5
1784 ; GFX11-IEEE-NEXT: v_mul_f32_e32 v7, v8, v4
1790 ; GFX11-IEEE-NEXT: v_fmac_f32_e32 v7, v10, v4
1796 ; GFX11-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v7
1810 ; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v0, 1.0
1818 ; GFX11-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
1819 ; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
1822 ; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
1824 ; GFX11-FLUSH-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
1827 ; GFX11-FLUSH-NEXT: v_rcp_f32_e32 v3, v4
1833 ; GFX11-FLUSH-NEXT: v_fma_f32 v5, -v4, v3, 1.0
1837 ; GFX11-FLUSH-NEXT: v_fma_f32 v6, -v4, v5, v2
1840 ; GFX11-FLUSH-NEXT: v_fma_f32 v2, -v4, v5, v2
1997 ; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
1998 ; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
2000 ; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
2003 ; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
2005 ; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
2006 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
2009 ; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
2011 ; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
2012 ; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
2013 ; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4
2015 ; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
2017 ; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6
2025 ; GCN-FLUSH-NEXT: v_mov_b32_e32 v4, 0x2f800000
2027 ; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v5, 1.0, v4, vcc
2029 ; GCN-FLUSH-NEXT: v_cndmask_b32_e32 v4, 1.0, v4, vcc
2031 ; GCN-FLUSH-NEXT: v_mul_f32_e32 v3, v3, v4
2037 ; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v1
2043 ; GFX89-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
2047 ; GFX89-IEEE-NEXT: v_rcp_f32_e32 v8, v4
2049 ; GFX89-IEEE-NEXT: v_fma_f32 v10, -v4, v8, 1.0
2055 ; GFX89-IEEE-NEXT: v_fma_f32 v12, -v4, v10, v6
2059 ; GFX89-IEEE-NEXT: v_fma_f32 v4, -v4, v10, v6
2061 ; GFX89-IEEE-NEXT: v_div_fmas_f32 v4, v4, v8, v10
2064 ; GFX89-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
2072 ; GFX10-IEEE-NEXT: v_div_scale_f32 v4, s4, v2, v2, v0
2075 ; GFX10-IEEE-NEXT: v_rcp_f32_e32 v6, v4
2077 ; GFX10-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
2084 ; GFX10-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
2088 ; GFX10-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
2090 ; GFX10-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
2093 ; GFX10-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
2102 ; GFX10-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s4
2104 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v2, v2, v4
2110 ; GFX10-FLUSH-NEXT: v_mul_f32_e32 v0, v4, v0
2119 ; GFX11-IEEE-NEXT: v_div_scale_f32 v4, null, v2, v2, v0
2123 ; GFX11-IEEE-NEXT: v_rcp_f32_e32 v6, v4
2126 ; GFX11-IEEE-NEXT: v_fma_f32 v8, -v4, v6, 1.0
2134 ; GFX11-IEEE-NEXT: v_fma_f32 v12, -v4, v9, v10
2140 ; GFX11-IEEE-NEXT: v_fma_f32 v4, -v4, v9, v10
2143 ; GFX11-IEEE-NEXT: v_div_fmas_f32 v4, v4, v6, v9
2147 ; GFX11-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
2158 ; GFX11-FLUSH-NEXT: v_cndmask_b32_e64 v4, 1.0, 0x2f800000, s0
2162 ; GFX11-FLUSH-NEXT: v_dual_mul_f32 v2, v2, v4 :: v_dual_mul_f32 v3, v3, v5
2168 ; GFX11-FLUSH-NEXT: v_dual_mul_f32 v0, v4, v0 :: v_dual_mul_f32 v1, v5, v1