| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | RegisterCoalescer.h | 60 CoalescerPair(const TargetRegisterInfo &tri) : TRI(tri) {} in CoalescerPair() argument
65 const TargetRegisterInfo &tri) in CoalescerPair() argument
66 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg) {} in CoalescerPair()
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| H A D | InterferenceCache.cpp | 54 const TargetRegisterInfo *tri) { in init() argument
57 TRI = tri; in init()
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| H A D | InterferenceCache.h | 169 const TargetRegisterInfo *tri);
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| H A D | BranchFolding.h | 45 const TargetRegisterInfo *tri,
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| H A D | LiveRangeEdit.cpp | 183 const TargetRegisterInfo &tri, in rematerializeAt() argument
186 TII.reMaterialize(MBB, MI, DestReg, 0, *RM.OrigMI, tri); in rematerializeAt()
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| H A D | RDFRegisters.cpp | 27 PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri, in PhysicalRegisterInfo() argument
29 : TRI(tri) { in PhysicalRegisterInfo()
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| H A D | MachineScheduler.cpp | 1540 const TargetRegisterInfo *tri, bool IsLoad) in BaseMemOpClusterMutation() argument
1541 : TII(tii), TRI(tri), IsLoad(IsLoad) {} in BaseMemOpClusterMutation()
1557 const TargetRegisterInfo *tri) in StoreClusterMutation() argument
1558 : BaseMemOpClusterMutation(tii, tri, false) {} in StoreClusterMutation()
1563 LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri) in LoadClusterMutation() argument
1564 : BaseMemOpClusterMutation(tii, tri, true) {} in LoadClusterMutation()
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| H A D | RDFGraph.cpp | 650 const TargetRegisterInfo &tri, const MachineDominatorTree &mdt, in DataFlowGraph() argument
652 : MF(mf), TII(tii), TRI(tri), PRI(tri, mf), MDT(mdt), MDF(mdf), TOI(toi), in DataFlowGraph()
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| H A D | BranchFolding.cpp | 184 const TargetRegisterInfo *tri, in OptimizeFunction() argument
193 TRI = tri; in OptimizeFunction()
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| H A D | RegisterCoalescer.cpp | 421 LLVM_NODISCARD static bool isMoveInstr(const TargetRegisterInfo &tri, in INITIALIZE_PASS_DEPENDENCY()
432 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(), in INITIALIZE_PASS_DEPENDENCY()
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| /llvm-project-15.0.7/flang/lib/Optimizer/Builder/Runtime/ |
| H A D | Character.cpp | 117 auto tri = builder.create<fir::CallOp>(loc, beginFunc, args).getResult(0); in genCharCompare() local
118 auto zero = builder.createIntegerConstant(loc, tri.getType(), 0); in genCharCompare()
119 return builder.create<mlir::arith::CmpIOp>(loc, cmp, tri, zero); in genCharCompare()
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.h | 31 HexagonEvaluator(const HexagonRegisterInfo &tri, MachineRegisterInfo &mri,
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| H A D | HexagonBitTracker.cpp | 40 HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri, in HexagonEvaluator() argument
44 : MachineEvaluator(tri, mri), MF(mf), MFI(mf.getFrameInfo()), TII(tii) { in HexagonEvaluator()
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| /llvm-project-15.0.7/llvm/include/llvm/CodeGen/ |
| H A D | RDFRegisters.h | 103 PhysicalRegisterInfo(const TargetRegisterInfo &tri,
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| H A D | RDFGraph.h | 646 const TargetRegisterInfo &tri, const MachineDominatorTree &mdt,
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| /llvm-project-15.0.7/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGRRList.cpp | 1770 const TargetRegisterInfo *tri, in RegReductionPQBase() argument
1773 SrcOrder(srcorder), MF(mf), TII(tii), TRI(tri), TLI(tli) { in RegReductionPQBase()
1781 RegLimit[RC->getID()] = tri->getRegPressureLimit(RC, MF); in RegReductionPQBase()
1896 const TargetRegisterInfo *tri, in RegReductionPriorityQueue() argument
1899 tii, tri, tli), in RegReductionPriorityQueue()
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| /llvm-project-15.0.7/mlir/include/mlir/Dialect/Transform/IR/ |
| H A D | TransformDialect.td | 171 Transformation application functions produce a tri-state status:
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| /llvm-project-15.0.7/llvm/docs/Proposals/ |
| H A D | VariableNames.rst | 150 TargetRegisterInfo tri
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