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/llvm-project-15.0.7/polly/lib/External/ppcg/
H A Dgpu_array_tile.c10 if (!tile) in gpu_array_tile_free()
13 for (j = 0; j < tile->n; ++j) { in gpu_array_tile_free()
19 free(tile->bound); in gpu_array_tile_free()
21 free(tile); in gpu_array_tile_free()
34 if (!tile) in gpu_array_tile_create()
37 tile->ctx = ctx; in gpu_array_tile_create()
39 if (!tile->bound) in gpu_array_tile_create()
42 tile->n = n_index; in gpu_array_tile_create()
46 tile->bound[i].lb = NULL; in gpu_array_tile_create()
51 return tile; in gpu_array_tile_create()
[all …]
H A Dgpu_group.c112 struct gpu_array_tile *tile; in gpu_array_ref_group_requires_unroll() local
115 if (!tile) in gpu_array_ref_group_requires_unroll()
649 if (i < tile->n) in compute_tile_depth()
753 tile->bound[i].lb = isl_aff_drop_dims(tile->bound[i].lb, in tile_adjust_depth()
755 if (!tile->bound[i].lb) in tile_adjust_depth()
759 tile->bound[i].shift = isl_aff_drop_dims(tile->bound[i].shift, in tile_adjust_depth()
765 tile->depth = depth; in tile_adjust_depth()
779 if (tile_adjust_depth(tile, compute_tile_depth(data, tile)) < 0) in tile_set_depth()
1794 if (!tile) in gpu_array_ref_group_compute_tiling()
1806 if (i < tile->n) in gpu_array_ref_group_compute_tiling()
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/llvm-project-15.0.7/clang/test/OpenMP/
H A Dtile_messages.cpp6 #pragma omp tile sizes in func()
11 #pragma omp tile sizes( in func()
15 #pragma omp tile sizes() in func()
19 #pragma omp tile sizes(5 in func()
24 #pragma omp tile sizes(5, in func()
28 #pragma omp tile sizes(5,) in func()
33 #pragma omp tile sizes(5+ in func()
37 #pragma omp tile sizes(5+) in func()
45 #pragma omp tile sizes(0) in func()
52 #pragma omp tile sizes(a) in func()
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H A Dtile_codegen.cpp20 #pragma omp tile sizes(5) in S()
28 #pragma omp tile sizes(5) in foo1()
34 #pragma omp tile sizes(5,5) in foo2()
42 #pragma omp tile sizes(5,5) in foo3()
51 #pragma omp tile sizes(5,5) in foo4()
60 #pragma omp tile sizes(5) in foo5()
69 #pragma omp tile sizes(5) in foo6()
77 #pragma omp tile sizes(Tile) in foo7()
H A Dtile_ast_print.cpp29 #pragma omp tile sizes(5,5) in foo1()
50 #pragma omp tile sizes(5,5) in foo2()
75 #pragma omp tile sizes(5) in foo3()
100 #pragma omp tile sizes(5, 5) in foo4()
132 #pragma omp tile sizes(5) in foo5()
150 #pragma omp tile sizes(Tile) in foo6()
173 #pragma omp tile sizes(Tile) in foo7()
/llvm-project-15.0.7/clang/lib/Headers/
H A Damxintrin.h133 #define _tile_zero(tile) __builtin_ia32_tilezero((tile)) argument
300 _tile1024i tile; member
362 dst->tile = _tile_dpbssd_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbssd()
363 src0.tile, src1.tile); in __tile_dpbssd()
385 dst->tile = _tile_dpbsud_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbsud()
386 src0.tile, src1.tile); in __tile_dpbsud()
408 dst->tile = _tile_dpbusd_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbusd()
409 src0.tile, src1.tile); in __tile_dpbusd()
431 dst->tile = _tile_dpbuud_internal(src0.row, src1.col, src0.col, dst->tile, in __tile_dpbuud()
432 src0.tile, src1.tile); in __tile_dpbuud()
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/llvm-project-15.0.7/mlir/test/Transforms/
H A Dnormalize-memrefs.mlir205 …_multiple_argument_type(%A: memref<16xf64, #tile>, %B: f64, %C: memref<8xf64, #tile>) -> (memref<8…
211 …l @ret_single_argument_type(%C) : (memref<8xf64, #tile>) -> (memref<16xf64, #tile>, memref<8xf64, …
229 …func @ret_single_argument_type(%C: memref<8xf64, #tile>) -> (memref<16xf64, #tile>, memref<8xf64, …
233 …l @ret_single_argument_type(%a) : (memref<8xf64, #tile>) -> (memref<16xf64, #tile>, memref<8xf64, …
234 …l @ret_single_argument_type(%C) : (memref<8xf64, #tile>) -> (memref<16xf64, #tile>, memref<8xf64, …
235 …le_argument_type(%b, %d, %a) : (memref<16xf64, #tile>, f64, memref<8xf64, #tile>) -> (memref<8xf64…
236 …ret_single_argument_type(%res1) : (memref<8xf64, #tile>) -> (memref<16xf64, #tile>, memref<8xf64, …
237 return %b, %a: memref<16xf64, #tile>, memref<8xf64, #tile>
303 func.func private @external_func_B(memref<16xf64, #tile>, f64) -> (memref<8xf64, #tile>)
316 func.func @use_value_of_external(%A: memref<16xf64, #tile>, %B: f64) -> (memref<8xf64, #tile>) {
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/llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/
H A Damx-fastconfig-spill.mir13 - { id: 2, class: tile }
16 - { id: 5, class: tile }
17 - { id: 6, class: tile }
18 - { id: 7, class: tile }
65 %2:tile = PTILEZEROV %1, %0
82 # Test tile copy fold
90 - { id: 2, class: tile }
93 - { id: 5, class: tile }
94 - { id: 6, class: tile }
95 - { id: 7, class: tile }
[all …]
H A Damx-fastpreconfig.mir15 - { id: 4, class: tile }
16 - { id: 5, class: tile }
17 - { id: 6, class: tile }
18 - { id: 7, class: tile }
39 …; CHECK-NEXT: [[PTILELOADDV:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1,…
40 …; CHECK-NEXT: [[PTILELOADDV1:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1…
41 …; CHECK-NEXT: [[PTILELOADDV2:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1…
52 %4:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg
53 %5:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg
54 %6:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg
[all …]
H A Damx-fastconfig.mir50 - { id: 0, class: tile }
51 - { id: 1, class: tile }
52 - { id: 2, class: tile }
53 - { id: 3, class: tile }
54 - { id: 4, class: tile }
55 - { id: 5, class: tile }
56 - { id: 6, class: tile }
57 - { id: 7, class: tile }
58 - { id: 8, class: tile }
71 - { id: 21, class: tile }
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H A Damx-fastconfig-phi.mir47 - { id: 1, class: tile }
48 - { id: 2, class: tile }
49 - { id: 3, class: tile }
50 - { id: 4, class: tile }
51 - { id: 5, class: tile }
53 - { id: 7, class: tile }
54 - { id: 8, class: tile }
55 - { id: 9, class: tile }
56 - { id: 10, class: tile }
75 - { id: 29, class: tile }
[all …]
H A Damx-fastconfig-phi4.mir21 - { id: 1, class: tile }
22 - { id: 2, class: tile }
23 - { id: 3, class: tile }
24 - { id: 4, class: tile }
58 ; CHECK-NEXT: %t0:tile = PTILEZEROV %r0, %c0
119 %t0:tile = PTILEZEROV %r0, %c0
128 %1:tile = PTILEZEROV killed %18, killed %17
132 %2:tile = PHI %t0, %bb.0, %3, %bb.3, %4, %bb.2
133 %5:tile = PHI %t0, %bb.0, %3, %bb.3, %2, %bb.2
136 %4:tile = PTILEZEROV killed %26, killed %25
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H A Dlat-combine-amx-bitcast.ll13 %tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0)
14 %1 = call x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32> %tmp)
45 %tmp = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %0)
50 %2 = call x86_amx @llvm.x86.cast.vector.to.tile.v616i8(<616 x i8> undef)
51 %3 = call x86_amx @llvm.x86.cast.vector.to.tile.v560i8(<560 x i8> undef)
53 %5 = call <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx %4)
374 declare <110 x i32> @llvm.x86.cast.tile.to.vector.v110i32(x86_amx)
375 declare <616 x i8> @llvm.x86.cast.tile.to.vector.v616i8(x86_amx)
376 declare x86_amx @llvm.x86.cast.vector.to.tile.v110i32(<110 x i32>)
378 declare x86_amx @llvm.x86.cast.vector.to.tile.v616i8(<616 x i8>)
[all …]
H A Damx-fastconfig-phi2.mir13 # This case test tile PHIs depend each other, and the its def block is
20 - { id: 1, class: tile }
21 - { id: 2, class: tile }
22 - { id: 3, class: tile }
23 - { id: 4, class: tile }
56 ; CHECK-NEXT: %t0:tile = PTILEZEROV %r0, %c0
71 ; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTILEZEROV [[MOV16ri1]], [[MOV16ri]]
110 %t0:tile = PTILEZEROV killed %r0, killed %c0
119 %1:tile = PTILEZEROV killed %18, killed %17
123 %2:tile = PHI %t0, %bb.0, %3, %bb.3
[all …]
H A Damx-tile-intrinsics.ll2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -verify-machineinstrs | FileCheck …
3 ; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mattr=+amx-tile -verify-machineinstrs | FileCh…
32 declare void @llvm.x86.tileloadd64(i8 %tile, ptr %base, i64 %stride)
33 declare void @llvm.x86.tileloaddt164(i8 %tile, ptr %base, i64 %stride)
34 declare void @llvm.x86.tilestored64(i8 %tile, ptr %base, i64 %stride)
38 declare void @llvm.x86.tilezero(i8 %tile)
H A Dlat-transform-amx-bitcast.ll18 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
29 %t = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %in)
46 %t2 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t1)
64 %t2 = call x86_amx @llvm.x86.cast.vector.to.tile.v225i32(<225 x i32> %t1)
82 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
100 %t = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %add)
141 %10 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %9)
342 declare x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32>)
343 declare x86_amx @llvm.x86.cast.vector.to.tile.v225i32(<225 x i32>)
344 declare <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx)
[all …]
H A Damx-combine.ll11 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
26 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
38 %t2 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t1)
52 %t2 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t1)
67 %t2 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t1)
69 %t3 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t2)
84 %t2 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t1)
86 %t3 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t2)
91 declare x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32>)
92 declare <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx)
H A Damx-combine-undef.ll27 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
36 %t5 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t4)
64 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
69 %t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
97 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
102 %t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
135 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
140 %t4 = call x86_amx @llvm.x86.cast.vector.to.tile.v256i32(<256 x i32> %t3)
175 %t2 = call <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx %t1)
265 declare <256 x i32> @llvm.x86.cast.tile.to.vector.v256i32(x86_amx)
[all …]
H A Damx-greedy-ra.ll4 ; Test the tile register is allocated in a seperate pass.
23 ; CHECK-NEXT: [[PTILEZEROV:%[0-9]+]]:tile = PTILEZEROV %13.sub_16bit, %12.sub_16bit
24 ; CHECK-NEXT: [[PTILEZEROV1:%[0-9]+]]:tile = PTILEZEROV %13.sub_16bit, %12.sub_16bit
25 ; CHECK-NEXT: [[PTILEZEROV2:%[0-9]+]]:tile = PTILEZEROV %13.sub_16bit, %12.sub_16bit
26 …; CHECK-NEXT: dead [[PTILEZEROV2]]:tile = PTDPBSSDV %13.sub_16bit, %12.sub_16bit, %12.sub_16bit,…
/llvm-project-15.0.7/mlir/include/mlir/Dialect/AMX/
H A DAMX.td13 // tile registers TMM0 through TMM7 (TILEDATA).
18 // and tile release.
44 tile registers TMM0 through TMM7 (TILEDATA).
84 let summary = "tile zero operation";
112 let summary = "tile load operation";
117 corresponding tile configuration.
143 let summary = "tile store operation";
148 corresponding tile configuration.
179 Multiplies a "m x k" tile with a "k x n" tile and accumulates the results
214 Multiplies a "m x k" tile with a "k x n" tile and accumulates the results
[all …]
/llvm-project-15.0.7/mlir/include/mlir/Interfaces/
H A DTilingInterface.td22 tile them (similar to LinalgOp, but without having access to
73 tile within this iteration space whose implementation the
79 - `offsets` provides the offset of the tile within the
81 - `sizes` provides the size of the tile.
128 Generates the IR that computes the tile of a result of the
129 operation. The `offsets` and `sizes` describe the tile of
132 implementation of the operation given a tile of the
134 implementation of the operation based on the tile of the
135 result required. This method enables fusion by using tile
144 - `offsets` provides the offset of the tile within the
[all …]
/llvm-project-15.0.7/mlir/test/Dialect/Linalg/
H A Dtile-parallel.mlir1 // RUN: mlir-opt %s -linalg-tile="tile-sizes=2 loop-type=parallel" | FileCheck %s -check-prefix=TIL…
2 // RUN: mlir-opt %s -linalg-tile="tile-sizes=0,2 loop-type=parallel" | FileCheck %s -check-prefix=T…
3 // RUN: mlir-opt %s -linalg-tile="tile-sizes=0,0,2 loop-type=parallel" | FileCheck %s -check-prefix…
4 // RUN: mlir-opt %s -linalg-tile="tile-sizes=2,3,4 loop-type=parallel" | FileCheck %s -check-prefix…
/llvm-project-15.0.7/clang/include/clang/Basic/
H A DBuiltinsX86_64.def109 TARGET_BUILTIN(__builtin_ia32_tile_loadconfig_internal, "vvC*", "n", "amx-tile")
110 TARGET_BUILTIN(__builtin_ia32_tileloadd64_internal, "V256iUsUsvC*z", "n", "amx-tile")
116 TARGET_BUILTIN(__builtin_ia32_tilestored64_internal, "vUsUsv*zV256i", "n", "amx-tile")
117 TARGET_BUILTIN(__builtin_ia32_tilezero_internal, "V256iUsUs", "n", "amx-tile")
120 TARGET_BUILTIN(__builtin_ia32_tile_loadconfig, "vvC*", "n", "amx-tile")
121 TARGET_BUILTIN(__builtin_ia32_tile_storeconfig, "vvC*", "n", "amx-tile")
122 TARGET_BUILTIN(__builtin_ia32_tilerelease, "v", "n", "amx-tile")
123 TARGET_BUILTIN(__builtin_ia32_tilezero, "vUc", "n", "amx-tile")
125 TARGET_BUILTIN(__builtin_ia32_tileloadd64, "vIUcvC*z", "n", "amx-tile")
126 TARGET_BUILTIN(__builtin_ia32_tileloaddt164, "vIUcvC*z", "n", "amx-tile")
[all …]
/llvm-project-15.0.7/polly/test/ScheduleOptimizer/
H A Drectangular-tiling.ll1 ; RUN: opt %loadPolly -polly-tile-sizes=256,16 …
2 ; RUN: opt %loadPolly -polly-tile-sizes=256,16 -polly-tiling=false …
3 ; RUN: opt %loadPolly -polly-tile-sizes=256,16 -polly-2nd-level-tiling -polly-2nd-level-tile-sizes=…
4 ; RUN: opt %loadPolly -polly-tile-sizes=256,16 -polly-2nd-level-tiling -polly-2nd-level-tile-sizes=…
5 …loadPolly -polly-tile-sizes=256,16 -polly-2nd-level-tiling -polly-2nd-level-tile-sizes=16,8 -polly…
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DSMEInstrFormats.td244 (ADDHA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
248 (ADDVA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
402 // tile registers.
488 (Inst $tile, $idx, $imm, $pg, $base, XZR)>;
493 (imm2tile untyped:$tile),
693 (inst imm_ty:$tile, $idx, 0, $pg, $zn)>;
698 (inst imm_ty:$tile, $idx, $imm, $pg, $zn)>;
750 // tile registers.
881 (inst $passthru, $pg, $tile, $idx, 0)>;
884 (imm2tile untyped:$tile),
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