Lines Matching refs:tile

32     : Pseudo<(outs), (ins i64imm:$tile, PPR3bAny:$pn, PPR3bAny:$pm,
72   def : Pat<(op imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
74             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
85   def : Pat<(op imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
87             (!cast<Instruction>(NAME # _PSEUDO) imm0_7:$tile, $pn, $pm, $zn, $zm)>;
128   def : Pat<(op imm0_3:$tile, (nxv16i1 PPR3bAny:$pn), (nxv16i1 PPR3bAny:$pm),
130             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
143   def : Pat<(op imm0_7:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
145             (!cast<Instruction>(NAME # _PSEUDO) imm0_7:$tile, $pn, $pm, $zn, $zm)>;
177   def : Pat<(op imm0_3:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
179             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
187   def : Pat<(op imm0_3:$tile, (nxv8i1 PPR3bAny:$pn), (nxv8i1 PPR3bAny:$pm),
189             (!cast<Instruction>(NAME # _PSEUDO) imm0_3:$tile, $pn, $pm, $zn, $zm)>;
232              (ins i64imm:$tile, PPR3bAny:$Pn, PPR3bAny:$Pm, zpr_ty:$Zn), []>,
242             imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
244           (ADDHA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
246             imm0_3:$tile, (nxv4i1 PPR3bAny:$pn), (nxv4i1 PPR3bAny:$pm),
248           (ADDVA_MPPZ_PSEUDO_S imm0_3:$tile, $pn, $pm, $zn)>;
255             imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
257           (ADDHA_MPPZ_PSEUDO_D imm0_7:$tile, $pn, $pm, $zn)>;
259             imm0_7:$tile, (nxv2i1 PPR3bAny:$pn), (nxv2i1 PPR3bAny:$pm),
261           (ADDVA_MPPZ_PSEUDO_D imm0_7:$tile, $pn, $pm, $zn)>;
339   def : Pat<(Load PPR3bAny:$pg, GPR64sp:$base, tile_ty:$tile,
341             (Inst tile_ty:$tile, $idx, $imm, $pg, $base, XZR)>;
346                     tile_ty:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$idx,
348               (Inst tile_ty:$tile, $idx, $imm, $pg, $base, $offset)>;
353     : Pseudo<(outs), (ins i64imm:$tile, MatrixIndexGPR32Op12_15:$idx,
402   // tile registers.
486   def : Pat<(Store PPR3bAny:$pg, GPR64sp:$base, (imm2tile untyped:$tile),
488             (Inst $tile, $idx, $imm, $pg, $base, XZR)>;
493                      (imm2tile untyped:$tile),
495               (Inst $tile, $idx, $imm, $pg, $base, $offset)>;
691   def : Pat<(op imm_ty:$tile, MatrixIndexGPR32Op12_15:$idx,
693             (inst imm_ty:$tile, $idx, 0, $pg, $zn)>;
695     def : Pat<(op imm_ty:$tile, (i32 (tileslice MatrixIndexGPR32Op12_15:$idx,
698               (inst imm_ty:$tile, $idx, $imm, $pg, $zn)>;
703     : Pseudo<(outs), (ins i64imm:$tile, MatrixIndexGPR32Op12_15:$idx,
750   // tile registers.
880                         (imm2tile untyped:$tile), MatrixIndexGPR32Op12_15:$idx)),
881             (inst $passthru, $pg, $tile, $idx, 0)>;
884                           (imm2tile untyped:$tile),
887               (inst $passthru, $pg, $tile, $idx, $imm)>;
1012 // the tile registers being zeroed. We fix this up in a custom inserter that