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/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl_mips64.S19 daddu $gp,$gp,$t9
50 ld $t9,0($t9)
51 jr $t9
71 daddu $gp,$gp,$t9
102 ld $t9,0($t9)
103 jr $t9
123 daddu $gp,$gp,$t9
156 ld $t9,0($t9)
157 jr $t9
210 ld $t9,0($t9)
[all …]
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_rtl_mips64.S19 daddu $gp,$gp,$t9
50 ld $t9,0($t9)
51 jr $t9
71 daddu $gp,$gp,$t9
102 ld $t9,0($t9)
103 jr $t9
123 daddu $gp,$gp,$t9
156 ld $t9,0($t9)
157 jr $t9
210 ld $t9,0($t9)
[all …]
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_mips.S23 .cpload $t9
37 la $t9, _ZN6__xray19XRayPatchedFunctionE
38 lw $t9, 0($t9)
40 beqz $t9, FunctionEntry_restore
46 jalr $t9
70 .cpload $t9
84 la $t9, _ZN6__xray19XRayPatchedFunctionE
85 lw $t9, 0($t9)
87 beqz $t9, FunctionExit_restore
93 jalr $t9
H A Dxray_trampoline_mips64.S46 daddu $gp, $gp, $t9
49 dla $t9, _ZN6__xray19XRayPatchedFunctionE
50 ld $t9, 0($t9)
52 beqz $t9, FunctionEntry_restore
58 jalr $t9
106 daddu $gp, $gp, $t9
109 dla $t9, _ZN6__xray19XRayPatchedFunctionE
110 ld $t9, 0($t9)
112 beqz $t9, FunctionExit_restore
118 jalr $t9
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
H A Dgloal_address_pic.mir48 liveins: $a0, $a1, $t9, $v0
51 ; MIPS32: liveins: $a0, $a1, $t9, $v0, $t9, $v0
52 ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
53 ; MIPS32: [[ADDu1:%[0-9]+]]:gpr32 = ADDu $v0, $t9
66 %4:gpr32 = ADDu $v0, $t9
89 liveins: $a0, $a1, $t9, $v0
92 ; MIPS32: liveins: $a0, $a1, $t9, $v0, $t9, $v0
93 ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
108 %4:gpr32 = ADDu $v0, $t9
132 ; MIPS32: liveins: $t9, $v0
[all …]
/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Damdgpu_isel.ll.expected25 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
26 ; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
41 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
42 ; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
57 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
58 ; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmidpoint-int.ll31 %t9 = mul nsw i32 %t8, %t4 ; signed
32 %a10 = add nsw i32 %t9, %a1 ; signed
54 %t9 = mul i32 %t8, %t4
55 %a10 = add i32 %t9, %a1
81 %t9 = mul nsw i32 %t8, %t4 ; signed
185 %t9 = mul i64 %t8, %t4
186 %a10 = add i64 %t9, %a1
318 %t9 = mul i16 %t8, %t4
319 %a10 = add i16 %t9, %a1
452 %t9 = mul i8 %t8, %t4
[all …]
H A Daarch64-checkMergeStoreCandidatesForDependencies.ll15 ; t9: i64,ch = load<(load (s64) from %ir.lp0, align 1)> t6, t8, undef:i64
17 ; t24: ch = TokenFactor t7:1, t9:1, t21
19 ; t19: i64,ch = load<(load (s64) from %ir.lp12, align 1, !tbaa !7)> t0, t9, undef:i64
23 ; t19 load depends on t9 (via address operand),
24 ; t9 load depends on the t6 store (via chain).
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcrash-lre-eliminate-dead-def.ll61 %t9.0 = phi i32 [ undef, %entry ], [ %t9.1, %for.end29 ], [ 0, %cleanup100 ]
95 %t9.1 = phi i32 [ %t9.2, %for.cond17 ], [ %t9.0, %if.end11 ]
101 %t9.2 = phi i32 [ undef, %for.cond20 ], [ %t9.1, %for.cond15 ]
130 %t9.6 = phi i32 [ %t9.1, %for.cond32thread-pre-split ], [ 0, %for.inc94 ]
177 %t9.8 = phi i32 [ 0, %cleanup100.L5_crit_edge ], [ undef, %if.then63 ], [ %t9.0, %if.end11 ]
179 store i32 %t9.8, ptr @s, align 4
186 %t9.9 = phi i32 [ %t9.8, %L5 ], [ undef, %if.then63 ]
209 %t9.12 = phi i32 [ %t9.6, %if.then36 ], [ undef, %cleanup75.thread128 ]
217 %t9.13 = phi i32 [ %t9.0, %if.then ], [ %t9.12, %if.end78 ]
H A Dvec_ins_extract-1.ll32 %t9 = extractelement <4 x i32> %t13, i32 0
33 ret i32 %t9
62 %t9 = extractelement <4 x i32> %t13, i32 %t7
63 ret i32 %t9
87 %t9 = extractelement <4 x i32> %t8, i32 %t7
88 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 0
115 %t9 = extractelement <4 x i32> %t8, i32 0
116 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
H A Dmidpoint-int.ll59 %t9 = mul nsw i32 %t8, %t4 ; signed
60 %a10 = add nsw i32 %t9, %a1 ; signed
109 %t9 = mul i32 %t8, %t4
110 %a10 = add i32 %t9, %a1
164 %t9 = mul nsw i32 %t8, %t4 ; signed
419 %t9 = mul i64 %t8, %t4
420 %a10 = add i64 %t9, %a1
763 %t9 = mul i16 %t8, %t4
764 %a10 = add i16 %t9, %a1
1045 %t9 = mul i8 %t8, %t4
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Dcopy-fp64.ll12 ; CHECK: liveins: $d12_64, $t9, $v0
13 ; CHECK: renamable $at = ADDu killed $v0, killed $t9
16 ; CHECK: renamable $t9 = LW killed renamable $at, target-flags(mips-got) @bar
17 …; CHECK: dead $ra = JALR killed $t9, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, impli…
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
H A Dglobal_address_pic.mir16 liveins: $a0, $a1, $t9, $v0
19 ; MIPS32: liveins: $a0, $a1, $t9, $v0
20 ; MIPS32: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
33 %4:gpr32 = ADDu $v0, $t9
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Deliminate-max.ll34 %t9 = sub i32 0, %t ; <i32> [#uses=3]
35 %t10 = icmp slt i32 %t9, 0 ; <i1> [#uses=1]
39 %t12 = icmp sgt i32 %t9, 255 ; <i1> [#uses=1]
40 %t13 = select i1 %t12, i32 255, i32 %t9 ; <i32> [#uses=1]
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dmightymul.ll14 %t9 = mul i32 %t8, %t8
15 %t10 = mul i32 %t9, %t9
H A Dfast-mightymul.ll14 %t9 = fmul fast float %t8, %t8
15 %t10 = fmul fast float %t9, %t9
/llvm-project-15.0.7/compiler-rt/test/asan/TestCases/Posix/
H A Dstack-overflow.cpp39 int t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13; in recursive_func()
49 t9 = z9; in recursive_func()
64 z9 = t9; in recursive_func()
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/
H A Dglobal_address_pic.ll23 ; MIPS32_PIC: liveins: $a0, $a1, $t9, $v0
24 ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
45 ; MIPS32_PIC: liveins: $a0, $a1, $t9, $v0
46 ; MIPS32_PIC: [[ADDu:%[0-9]+]]:gpr32 = ADDu $v0, $t9
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dcmse-clear-return.c147 T9 t9; variable
148 __attribute__((cmse_nonsecure_entry)) T9 f9(void) { return t9; } in f9()
154 T9 f91(void) { return t9; } in f91()
H A Dms_struct-bitfield-1.c79 } ATTR t9; variable
80 static int a9[(sizeof(t9) == 16) -1];
H A Darm-aapcs-zerolength-bitfield.c82 struct t9 struct
89 static int arr9_offset[(offsetof(struct t9, bar2) == 5) ? 0 : -1]; argument
90 static int arr9_sizeof[(sizeof(struct t9) == 8) ? 0 : -1];
H A Darm-apcs-zerolength-bitfield.c86 struct t9 struct
93 static int arr9_offset[(offsetof(struct t9, bar2) == 5) ? 0 : -1]; argument
94 static int arr9_sizeof[(sizeof(struct t9) == 8) ? 0 : -1];
/llvm-project-15.0.7/llvm/test/CodeGen/Hexagon/vect/
H A Dvect-bool-basic-compile.ll36 %t9 = bitcast <8 x i1> %t8 to i8
37 %ta = zext i8 %t9 to i32
52 %t9 = insertelement <8 x i1> %t8, i1 %t1, i32 1
53 %ta = insertelement <8 x i1> %t9, i1 %t2, i32 2
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Daarch64-aapcs-zerolength-bitfield.cpp83 struct t9 struct
90 static_assert(offsetof(struct t9, bar2) == 9); argument
91 static_assert(sizeof(struct t9) == 16);
/llvm-project-15.0.7/llvm/test/CodeGen/MIR/Mips/
H A Dmemory-operands.mir55 $t9 = COPY $v1
57 …JumpLinkReg16 killed $v1, csr_o32, implicit-def $ra, implicit killed $t9, implicit $a0, implicit k…
97 $t9 = COPY $v1
99 …JumpLinkReg16 killed $v1, csr_mips16rethelper, implicit-def $ra, implicit killed $t9, implicit $v0…

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