Home
last modified time | relevance | path

Searched refs:t7 (Results 1 – 25 of 391) sorted by relevance

12345678910>>...16

/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dcrash-lre-eliminate-dead-def.ll94 %t7.1 = phi i16 [ %t7.2, %for.cond17 ], [ %t7.0, %if.end11 ]
100 %t7.2 = phi i16 [ %t7.3, %for.cond20 ], [ %t7.1, %for.cond15 ]
106 %t7.3 = phi i16 [ %t7.4, %for.cond23 ], [ %t7.2, %for.cond17 ]
111 %t7.4 = phi i16 [ %t7.5, %L1 ], [ %t7.3, %for.cond20 ]
116 %t7.5 = phi i16 [ %t7.19, %cleanup100 ], [ %t7.4, %for.cond23 ]
175 %t7.10 = phi i16 [ %t7.19, %cleanup100.L5_crit_edge ], [ %t7.9, %if.then63 ], [ %t7.0, %if.end11 ]
184 %t7.11 = phi i16 [ %t7.10, %L5 ], [ %t7.9, %if.then63 ]
192 %t7.12 = phi i16 [ %t7.11, %if.end67 ], [ %t7.9, %if.end61 ]
215 %t7.15 = phi i16 [ %t7.0, %if.then ], [ %t7.14, %if.end78 ]
233 %t7.17 = phi i16 [ %t7.6, %for.body34 ], [ %t7.15, %L6 ], [ %t7.15, %while.end.split ]
[all …]
H A Dvec_ins_extract-1.ll8 define i32 @t0(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
31 %t13 = insertelement <4 x i32> %t8, i32 76, i32 %t7
36 define i32 @t1(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
62 %t9 = extractelement <4 x i32> %t13, i32 %t7
66 define <4 x i32> @t2(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
87 %t9 = extractelement <4 x i32> %t8, i32 %t7
92 define <4 x i32> @t3(i32 inreg %t7, <4 x i32> inreg %t8) nounwind {
116 %t13 = insertelement <4 x i32> %t8, i32 %t9, i32 %t7
H A Dmasked-iv-safe.ll42 %t7 = load double, ptr %t6
43 %t8 = fmul double %t7, 4.5
88 %t7 = load double, ptr %t6
89 %t8 = fmul double %t7, 4.5
136 %t7 = load double, ptr %t6
137 %t8 = fmul double %t7, 4.5
184 %t7 = load double, ptr %t6
185 %t8 = fmul double %t7, 4.5
234 %t7 = load double, ptr %t6
235 %t8 = fmul double %t7, 4.5
[all …]
H A Dmidpoint-int.ll57 %t7 = sub i32 %t6, %t5
58 %t8 = lshr i32 %t7, 1
107 %t7 = sub i32 %t6, %t5
108 %t8 = lshr i32 %t7, 1
162 %t7 = sub i32 %t6, %t5
163 %t8 = lshr i32 %t7, 1
215 %t7 = sub i32 %t6, %t5
216 %t8 = lshr i32 %t7, 1
272 %t8 = lshr i32 %t7, 1
348 %t8 = lshr i64 %t7, 1
[all …]
H A Dmasked-iv-unsafe.ll49 %t7 = load double, ptr %t6
50 %t8 = fmul double %t7, 4.5
103 %t7 = load double, ptr %t6
104 %t8 = fmul double %t7, 4.5
163 %t7 = load double, ptr %t6
164 %t8 = fmul double %t7, 4.5
223 %t7 = load double, ptr %t6
224 %t8 = fmul double %t7, 4.5
277 %t7 = load double, ptr %t6
506 %t7 = load double, ptr %t6
[all …]
/llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/
H A Damdgpu_isel.ll.expected24 ; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
25 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
40 ; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
41 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
56 ; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
57 ; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
H A Dx86_isel.ll.expected10 ; PIC-NEXT: t7: i64,i32,ch = ADD64rm<Mem:(dereferenceable load (s64) from %ir.loc)> t2, TargetFr…
11 ; PIC-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
19 ; WIN-NEXT: t7: i64,i32,ch = ADD64rm<Mem:(dereferenceable load (s64) from %ir.loc)> t2, TargetFr…
20 ; WIN-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
34 ; PIC-NEXT: t7: i32,i32,ch = ADD32rm<Mem:(dereferenceable load (s32) from %ir.loc)> t2, TargetFr…
35 ; PIC-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6>
44 ; WIN-NEXT: t7: i32,i32,ch = ADD32rm<Mem:(dereferenceable load (s32) from %ir.loc)> t2, TargetFr…
45 ; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6>
74 ; WIN-NEXT: t14: i32 = MOVZX32rr16 t7
103 ; WIN-NEXT: t7: i8,i32,ch = ADD8rm<Mem:(dereferenceable load (s8) from %ir.loc)> t2, TargetFrame…
[all …]
/llvm-project-15.0.7/llvm/test/Assembler/
H A Dmulti-mod-disassemble.ll8 ; RUN: llvm-dis -o %t7.o %t6.o
9 ; RUN: diff %t7.o.0 %t7.o.1
10 ; RUN: FileCheck < %t7.o.0 %s
11 ; RUN: FileCheck < %t7.o.1 %s
H A Dmulti-summary-disassemble.ll8 ; RUN: llvm-dis -o %t7.o %t6.o
9 ; RUN: diff %t7.o.0 %t7.o.1
10 ; RUN: FileCheck < %t7.o.0 %s
11 ; RUN: FileCheck < %t7.o.1 %s
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Dmidpoint-int.ll29 %t7 = sub i32 %t6, %t5
30 %t8 = lshr i32 %t7, 1
52 %t7 = sub i32 %t6, %t5
53 %t8 = lshr i32 %t7, 1
79 %t7 = sub i32 %t6, %t5
80 %t8 = lshr i32 %t7, 1
104 %t7 = sub i32 %t6, %t5
105 %t8 = lshr i32 %t7, 1
132 %t8 = lshr i32 %t7, 1
161 %t8 = lshr i64 %t7, 1
[all …]
/llvm-project-15.0.7/compiler-rt/lib/sanitizer_common/tests/
H A Dsanitizer_bvgraph_test.cpp269 BV t7; in ShortestPath() local
270 t7.clear(); in ShortestPath()
271 t7.setBit(7); in ShortestPath()
281 EXPECT_TRUE(g.isReachable(1, t7)); in ShortestPath()
283 EXPECT_EQ(0U, g.findPath(1, t7, path, 1)); in ShortestPath()
285 EXPECT_EQ(2U, g.findPath(1, t7, path, 2)); in ShortestPath()
286 EXPECT_EQ(2U, g.findPath(1, t7, path, 3)); in ShortestPath()
287 EXPECT_EQ(2U, g.findPath(1, t7, path, 4)); in ShortestPath()
288 EXPECT_EQ(2U, g.findPath(1, t7, path, 5)); in ShortestPath()
289 EXPECT_EQ(2U, g.findPath(1, t7, path, 6)); in ShortestPath()
[all …]
/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmips64-register-names-n32-n64.s31 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
36 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
41 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
46 # WARNING: mips64-register-names-n32-n64.s:[[@LINE+4]]:9: warning: register names $t4-$t7 are only …
47 # WARNING-NEXT: daddiu $t7, $zero, 0 # {{CHECK}}: encoding: [0x64,0x0f,0x00,0x00]
50 daddiu $t7, $zero, 0 # CHECK: encoding: [0x64,0x0f,0x00,0x00]
69 # [*] - t0-t3 are aliases of t4-t7 for compatibility with both the original
70 # ABI documentation (using t4-t7) and GNU As (using t0-t3)
/llvm-project-15.0.7/llvm/test/Transforms/LICM/
H A Dloopsink.ll61 %t7 = add nuw nsw i32 %iv, 1
62 %c7 = icmp eq i32 %t7, %p7
128 %t7 = add nuw nsw i32 %iv, 1
129 %c7 = icmp eq i32 %t7, %p7
190 %t7 = add nuw nsw i32 %iv, 1
191 %c7 = icmp eq i32 %t7, %p7
275 %t7 = add nuw nsw i32 %iv, 1
276 %c7 = icmp eq i32 %t7, %p7
339 %t7 = add nuw nsw i32 %iv, 1
340 %c7 = icmp eq i32 %t7, %p7
[all …]
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Float/
H A Df-memory.s16 # ASM-AND-OBJ: fst.s $fs6, $t7, 230
18 fst.s $fs6, $t7, 230
20 # ASM-AND-OBJ: fldx.s $fa1, $t3, $t7
22 fldx.s $fa1, $t3, $t7
/llvm-project-15.0.7/cross-project-tests/debuginfo-tests/clang_llvm_roundtrip/
H A Dsimplified_template_names.cpp147 struct t7;
148 using t7i = t7<int>;
152 t7 { struct
287 struct t7 { }; in main() struct
288 f1<t7>(); in main()
338 struct t7 { }; in mem() struct
339 f1<t7>(); in mem()
/llvm-project-15.0.7/lldb/test/API/functionalities/data-formatter/data-formatter-objc/cmtime/
H A Dmain.m15 CMTime t7 = CMTimeMake(10, 1);
16 t7.flags = kCMTimeFlags_Indefinite;
24 CMTimeShow(t7);
/llvm-project-15.0.7/llvm/test/MC/LoongArch/Basic/Integer/
H A Darith.s20 # CHECK-ASM-AND-OBJ: sub.w $r21, $s2, $t7
22 sub.w $r21, $s2, $t7
68 # CHECK-ASM-AND-OBJ: and $t7, $s8, $ra
70 and $t7, $s8, $ra
80 # CHECK-ASM-AND-OBJ: xor $t3, $t7, $a4
82 xor $t3, $t7, $a4
124 # CHECK-ASM-AND-OBJ: div.wu $t7, $s0, $zero
126 div.wu $t7, $s0, $zero
155 # CHECK64-ASM-AND-OBJ: alsl.wu $t7, $a4, $s2, 1
157 alsl.wu $t7, $a4, $s2, 1
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dand-xor-merge.ll13 %t7 = xor i32 %t3, %t6
14 ret i32 %t7
25 %t7 = xor i32 %t3, %t6
26 ret i32 %t7
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-b.ll48 %t7 = shl i32 %t6, %t4
49 ret i32 %t7
89 ret <8 x i32> %t7
124 ret <8 x i32> %t7
159 ret <8 x i32> %t7
195 %t7 = shl i32 %t6, %t4
196 ret i32 %t7
234 %t7 = shl i32 %t6, %t4
235 ret i32 %t7
271 ret i32 %t7
[all …]
H A Dpartally-redundant-left-shift-input-masking-after-truncation-variant-a.ll48 %t7 = shl i32 %t6, %t4
49 ret i32 %t7
89 ret <8 x i32> %t7
124 ret <8 x i32> %t7
159 ret <8 x i32> %t7
197 %t7 = shl i32 %t6, %t4
198 ret i32 %t7
233 %t7 = shl i32 %t6, %t4
234 ret i32 %t7
271 %t7 = shl i32 %t6, %t4
[all …]
/llvm-project-15.0.7/clang/test/SemaCUDA/
H A Dasm_delayed_diags.cu67 static __device__ __host__ void t7(__m256i *p) { in t7() function
81 t7(0); in m()
96 t7(0); in main()
/llvm-project-15.0.7/llvm/test/Transforms/LoopVectorize/
H A Dfloat-minmax-instruction-flag.ll31 %t1 = phi i64 [ %t7, %loop ], [ 1, %top ]
37 %t7 = add i64 %t1, 1
38 %t8 = icmp eq i64 %t7, 65537
97 %t1 = phi i64 [ %t7, %loop ], [ 1, %top ]
103 %t7 = add i64 %t1, 1
104 %t8 = icmp eq i64 %t7, 65537
137 %t1 = phi i64 [ %t7, %loop ], [ 1, %top ]
143 %t7 = add i64 %t1, 1
144 %t8 = icmp eq i64 %t7, 65537
183 %t7 = add i64 %t1, 1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/Reassociate/
H A Dmightymul.ll12 %t7 = mul i32 %t6, %t6
13 %t8 = mul i32 %t7, %t7
/llvm-project-15.0.7/compiler-rt/test/asan/TestCases/Posix/
H A Dstack-overflow.cpp39 int t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13; in recursive_func()
47 t7 = z7; in recursive_func()
62 z7 = t7; in recursive_func()
/llvm-project-15.0.7/lld/test/ELF/
H A Dversion-script-complex-wildcards.s40 # RUN: echo "FOO { global: extern \"C++\" { ab[^c-z]*; }; };" > %t7.script
41 # RUN: ld.lld --version-script %t7.script -shared %t.o -o %t7.so
42 # RUN: llvm-readobj -V %t7.so | FileCheck %s --check-prefix=ABB

12345678910>>...16