| /llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/X86/ |
| H A D | pr52253.ll | 9 define i1 @foo(i32 %t4, i32 %t10) {
13 %t09 = shl i32 %t10, 24
25 define i1 @bar(i32 %t4, i32 %t10) {
29 %t09 = shl i32 %t10, 24
41 define i1 @foobar(i32 %t4, i32 %t10) {
45 %t09 = shl i32 %t10, 24
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| /llvm-project-15.0.7/llvm/test/Transforms/SCCP/ |
| H A D | pr52253.ll | 4 define i1 @foo(i32 %t4, i32 %t10) {
16 %t09 = shl i32 %t10, 24
28 define i1 @bar(i32 %t4, i32 %t10) {
40 %t09 = shl i32 %t10, 24
52 define i1 @foobar(i32 %t4, i32 %t10) {
66 %t09 = shl i32 %t10, 24
|
| /llvm-project-15.0.7/clang/test/CodeGen/ |
| H A D | windows-seh-abnormal-exits.c | 15 goto t10; // abnormal termination in seh_abnormal_exits()
26 t10:; in seh_abnormal_exits()
|
| H A D | ms_struct-bitfield-1.c | 90 } ATTR t10; variable
91 static int a10[(sizeof(t10) == 2) -1];
|
| H A D | arm-aapcs-zerolength-bitfield.c | 92 struct t10 struct
99 static int arr10_offset[(offsetof(struct t10, bar2) == 9) ? 0 : -1]; argument
100 static int arr10_sizeof[(sizeof(struct t10) == 16) ? 0 : -1];
|
| H A D | arm-apcs-zerolength-bitfield.c | 96 struct t10 struct
103 static int arr10_offset[(offsetof(struct t10, bar2) == 5) ? 0 : -1]; argument
104 static int arr10_sizeof[(sizeof(struct t10) == 8) ? 0 : -1];
|
| H A D | ms_struct-bitfield.c | 147 } ATTR t10; variable
148 int s10 = sizeof(t10);
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| H A D | attributes.c | 73 void t10(void) __attribute__((section("xSECT")));
74 void t10(void) {} in t10() function
|
| /llvm-project-15.0.7/llvm/test/Transforms/Reassociate/ |
| H A D | mightymul.ll | 15 %t10 = mul i32 %t9, %t9
16 %t11 = mul i32 %t10, %t10
|
| H A D | fast-mightymul.ll | 15 %t10 = fmul fast float %t9, %t9
16 %t11 = fmul fast float %t10, %t10
|
| /llvm-project-15.0.7/compiler-rt/test/asan/TestCases/Posix/ |
| H A D | stack-overflow.cpp | 39 int t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13; in recursive_func()
50 t10 = z10; in recursive_func()
65 z10 = t10; in recursive_func()
|
| /llvm-project-15.0.7/llvm/test/tools/llvm-objcopy/ELF/ |
| H A D | strip-all.test | 44 # RUN: cp %t %t10
45 # RUN: llvm-strip --strip-all --keep-symbol=unavailable_symbol %t10
46 # RUN: llvm-strip --strip-all --keep-symbol=unavailable_symbol %t10
47 # RUN: cmp %t2 %t10
|
| H A D | change-entry-point.test | 21 # RUN: llvm-objcopy --change-start -0x1101 %t %t10
22 # RUN: cmp %t9 %t10
35 # RUN: cmp %t10 %t14
|
| /llvm-project-15.0.7/llvm/test/Analysis/ScalarEvolution/ |
| H A D | sext-mul.ll | 50 ; CHECK: %t10 = ashr exact i128 %t9, 1
52 ; CHECK: %t14 = or i128 %t10, 1
76 %t10 = ashr exact i128 %t9, 1
77 %t11 = getelementptr inbounds i32, i32* %arg3, i128 %t10
81 %t14 = or i128 %t10, 1
|
| /llvm-project-15.0.7/clang/test/CodeGenCXX/ |
| H A D | aarch64-aapcs-zerolength-bitfield.cpp | 93 struct t10 struct
100 static_assert(offsetof(struct t10, bar2) == 9); argument
101 static_assert(sizeof(struct t10) == 16);
|
| /llvm-project-15.0.7/clang/test/Analysis/ |
| H A D | free.c | 65 void t10 (void) { in t10() function
66 free((void*)&t10); in t10()
|
| H A D | weak-functions.c | 73 void t10 (void) { in t10() function
74 free((void*)&t10); in t10()
|
| /llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/ |
| H A D | pr52275.ll | 62 %t10 = insertelement <2 x i8> %t8, i8 %t9, i64 1
63 %t11 = add <2 x i8> %t10, %t8
96 %t10 = insertelement <2 x i8> %t8, i8 %t9, i64 0
97 %t11 = add <2 x i8> %t10, %t8
130 %t10 = insertelement <4 x i8> %t8, i8 %t9, i64 1
131 %t11 = add <4 x i8> %t10, %t8
164 %t10 = insertelement <4 x i8> %t8, i8 %t9, i64 2
165 %t11 = add <4 x i8> %t10, %t8
|
| /llvm-project-15.0.7/clang/test/Sema/ |
| H A D | function.c | 29 void t10(){} in t10() function
30 void t11(){t10(1);} // expected-warning{{too many arguments}} in t11()
|
| /llvm-project-15.0.7/llvm/test/Transforms/InstCombine/ |
| H A D | 2009-07-02-MaskedIntVector.ll | 10 %t10 = bitcast i64 %t9 to <2 x i32> ; <<2 x i32>> [#uses=1]
12 %t6 = xor <2 x i32> %t10, %t7 ; <<2 x i32>> [#uses=1]
|
| /llvm-project-15.0.7/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ |
| H A D | x86_isel.ll.expected | 11 ; PIC-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
12 ; PIC-NEXT: t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1
20 ; WIN-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7
21 ; WIN-NEXT: t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1
|
| H A D | amdgpu_isel.ll.expected | 26 ; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
42 ; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
58 ; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
|
| /llvm-project-15.0.7/flang/test/Fir/ |
| H A D | array-coor.fir | 19 // CHECK: %[[t10:.*]] = load ptr, ptr %[[t9]]
20 // CHECK: %[[t11:.*]] = getelementptr i8, ptr %[[t10]], i64 %[[t8]]
|
| /llvm-project-15.0.7/llvm/test/CodeGen/X86/ |
| H A D | avx512-adc-sbb.ll | 23 %t10 = zext i1 %t9 to i8
24 %t11 = add i8 %t7, %t10
|
| /llvm-project-15.0.7/lld/test/ELF/linkerscript/ |
| H A D | sort.s | 90 # RUN: ld.lld --sort-section name -o %t10 --script %t9.script %t2.o %t1.o
91 # RUN: llvm-objdump -s %t10 | FileCheck --check-prefix=UNSORTED %s
94 # RUN: echo "SECTIONS { .aaa : { *(SORT_BY_NAME(SORT_NONE(.aaa.*))) } }" > %t10.script
95 # RUN: ld.lld -o %t11 --script %t10.script %t2.o %t1.o
|