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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dxnack-subtarget-feature-any.ll1 ; RUN: llc -march=amdgcn -mcpu=gfx600 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
2 ; RUN: llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
3 ; RUN: llc -march=amdgcn -mcpu=gfx801 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
5 ; RUN: llc -march=amdgcn -mcpu=gfx902 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
6 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --chec…
7 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --chec…
11 ; NOT-SUPPORTED: xnack setting for subtarget: Unsupported
12 ; ANY: xnack setting for subtarget: Any
13 define void @xnack-subtarget-feature-any() #0 {
H A Dxnack-subtarget-feature-disabled.ll1 ; RUN: llc -march=amdgcn -mcpu=gfx600 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck…
2 ; RUN: llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck…
3 ; RUN: llc -march=amdgcn -mcpu=gfx801 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
5 ; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
6 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --chec…
7 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --chec…
12 ; OFF: xnack setting for subtarget: Off
14 define void @xnack-subtarget-feature-disabled() #0 {
H A Dxnack-subtarget-feature-enabled.ll1 ; RUN: llc -march=amdgcn -mcpu=gfx600 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck…
2 ; RUN: llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o /dev/null %s 2>&1 | FileCheck…
3 ; RUN: llc -march=amdgcn -mcpu=gfx801 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
5 ; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
6 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --chec…
7 ; RUN: llc -march=amdgcn -mcpu=gfx1100 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --chec…
12 ; ON: xnack setting for subtarget: On
13 define void @xnack-subtarget-feature-enabled() #0 {
H A Dsramecc-subtarget-feature-any.ll1 ; RUN: llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
2 ; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
3 ; RUN: llc -march=amdgcn -mcpu=gfx908 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
7 ; NOT-SUPPORTED: sramecc setting for subtarget: Unsupported
8 ; ANY: sramecc setting for subtarget: Any
9 define void @sramecc-subtarget-feature-default() #0 {
H A Dsramecc-subtarget-feature-enabled.ll1 ; RUN: llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
2 ; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
3 ; RUN: llc -march=amdgcn -mcpu=gfx908 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
8 ; ON: sramecc setting for subtarget: On
9 define void @sramecc-subtarget-feature-enabled() #0 {
H A Dsramecc-subtarget-feature-disabled.ll1 ; RUN: llc -march=amdgcn -mcpu=gfx700 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
2 ; RUN: llc -march=amdgcn -mcpu=gfx906 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
3 ; RUN: llc -march=amdgcn -mcpu=gfx908 -debug-only=amdgpu-subtarget -o - %s 2>&1 | FileCheck --check…
8 ; OFF: sramecc setting for subtarget: Off
10 define void @sramecc-subtarget-feature-disabled() #0 {
H A Dread-register-invalid-subtarget.ll3 ; CHECK: invalid register "flat_scratch_lo" for subtarget.
H A Dllvm.amdgcn.log.clamp.ll4 ; ERR: intrinsic not supported on subtarget
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/
H A Dsections.ll32 ; CHECK-8515: error: Current AVR subtarget does not support accessing extended program memory
33 ; CHECK-tiny40: error: Current AVR subtarget does not support accessing program memory
38 ; CHECK-8515: error: Current AVR subtarget does not support accessing extended program memory
39 ; CHECK-tiny40: error: Current AVR subtarget does not support accessing program memory
44 ; CHECK-8515: error: Current AVR subtarget does not support accessing extended program memory
45 ; CHECK-tiny40: error: Current AVR subtarget does not support accessing program memory
50 ; CHECK-8515: error: Current AVR subtarget does not support accessing extended program memory
51 ; CHECK-tiny40: error: Current AVR subtarget does not support accessing program memory
56 ; CHECK-8515: error: Current AVR subtarget does not support accessing extended program memory
57 ; CHECK-tiny40: error: Current AVR subtarget does not support accessing program memory
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dfixup-per-fragment.s3 @ The relaxations should be applied using the subtarget from the fragment
4 @ containing the fixup and not the per module subtarget.
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td36 class EXP_Real_ComprVM<bit done, string pseudo, int subtarget>
39 SIMCInstr<pseudo, subtarget> {
44 class EXP_Real_Row<bit row, bit done, string pseudo, int subtarget>
47 SIMCInstr<pseudo, subtarget> {
H A DLDSDIRInstructions.td77 class LDSDIR_Real<bits<2> op, LDSDIR_Pseudo lds, int subtarget> :
81 SIMCInstr <lds.Mnemonic, subtarget>,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZ.td16 // SystemZ subtarget features
22 // SystemZ subtarget scheduling models
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DLeonFeatures.td17 //support to casa instruction; for leon3 subtarget only
31 //support to casa instruction; for leon3 subtarget only
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DBUILD.gn29 args = [ "-gen-subtarget" ]
59 args = [ "-gen-subtarget" ]
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSchedule.td26 // each subtarget, define WriteRes and ReadAdvance to associate
30 // subtarget, define ItinRW entries to map ItineraryClass to
32 // be subtarget specific and can be directly associated with resources
35 // C. In the subtarget, map SchedReadWrite types to specific
38 // subtarget can directly associate resources with SchedReadWrite
41 // D. In either the target or subtarget, define SchedWriteVariant or
273 // defined by the subtarget, and maps the SchedWrite to processor
279 // itinerary classes to the subtarget's SchedWrites.
425 // the subtarget to easily override specific operations.
432 // Allow a subtarget to mark some instructions as unsupported.
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/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARM.td109 // True if subtarget supports half-precision FP conversions.
120 // True if subtarget supports half-precision FP operations.
126 // True if subtarget supports half-precision FP fml operations.
132 // True if subtarget supports [su]div in Thumb mode.
137 // True if subtarget supports [su]div in ARM mode.
148 // True if the subtarget supports CLREX instructions.
424 // True if the subtarget has a branch predictor. Having
453 // True if the subtarget disallows unaligned memory
518 // True if subtarget supports 8-bit integer matrix multiply.
588 // True if subtarget does not support ARM mode execution.
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Ddivmod-hwdiv.ll1 ; The hwdiv subtarget feature should only influence thumb, not arm.
7 ; The hwdiv-arm subtarget feature should only influence arm, not thumb.
/llvm-project-15.0.7/llvm/test/MC/Disassembler/AMDGPU/
H A Dsi-support.txt3 # CHECK: LLVM ERROR: Disassembly not yet supported for subtarget
/llvm-project-15.0.7/llvm/test/MC/X86/AlignedBundling/
H A Dbundle-subtarget-change-error.s4 # Switching mode will change subtarget, which we can't do within a bundle
/llvm-project-15.0.7/llvm/test/TableGen/
H A DSchedModelError.td1 // RUN: not llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s -DFILE=%s
H A DCodeGenSchedule-duplicate-instrw.td1 // RUN: not llvm-tblgen --gen-subtarget -I %p/../../include -I %p/Common %s -o - 2>&1 | FileCheck %s
/llvm-project-15.0.7/llvm/lib/Target/DirectX/
H A DCMakeLists.txt5 tablegen(LLVM DirectXGenSubtargetInfo.inc -gen-subtarget)
/llvm-project-15.0.7/llvm/test/CodeGen/Generic/
H A Dinline-asm-mem-clobber.ll3 ; XCore default subtarget does not support 8-byte alignment on stack.
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DCMakeLists.txt11 tablegen(LLVM ARCGenSubtargetInfo.inc -gen-subtarget)

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