Lines Matching refs:subtarget

59 // True if subtarget has the full 32 double precision FP registers for VFPv3.
109 // True if subtarget supports half-precision FP conversions.
120 // True if subtarget supports half-precision FP operations.
126 // True if subtarget supports half-precision FP fml operations.
132 // True if subtarget supports [su]div in Thumb mode.
137 // True if subtarget supports [su]div in ARM mode.
144 // True if the subtarget supports DMB / DSB data barrier instructions.
148 // True if the subtarget supports CLREX instructions.
152 // True if the subtarget supports DFB data barrier instruction.
156 // True if the subtarget supports v8 atomics (LDA/LDAEX etc) instructions.
424 // True if the subtarget has a branch predictor. Having
432 /// True if the subtarget supports the DSP (saturating arith and such) instructions.
437 // True if the subtarget supports Multiprocessing extension (ARMv7 only).
453 // True if the subtarget disallows unaligned memory
493 // Use the MachineScheduler for instruction scheduling for the subtarget.
497 // Use the MachinePipeliner for instruction scheduling for the subtarget.
514 // True if subtarget supports BFloat16 floating point operations.
518 // True if subtarget supports 8-bit integer matrix multiply.
588 // True if subtarget does not support ARM mode execution.
733 // ARM Processor subtarget features.