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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dpr51516.mir32 undef %12.sub3:vreg_128 = V_ASHRREV_I32_e32 31, %11.sub3, implicit $exec
36 undef %14.sub3:vreg_128 = V_ASHRREV_I32_e32 31, %10.sub3, implicit $exec
40 undef %16.sub3:vreg_128 = V_ASHRREV_I32_e32 31, %9.sub3, implicit $exec
44 undef %18.sub3:vreg_128 = V_ASHRREV_I32_e32 31, %8.sub3, implicit $exec
48 undef %20.sub3:vreg_128 = V_ASHRREV_I32_e32 31, %7.sub3, implicit $exec
52 undef %22.sub3:vreg_128 = V_ASHRREV_I32_e32 31, %6.sub3, implicit $exec
56 undef %24.sub3:vreg_128 = V_ASHRREV_I32_e32 31, %5.sub3, implicit $exec
60 undef %26.sub3:vreg_128 = V_ASHRREV_I32_e32 31, %4.sub3, implicit $exec
68 %26.sub2:vreg_128 = COPY %4.sub3
74 %24.sub2:vreg_128 = COPY %5.sub3
[all …]
H A Dsplitkit-copy-live-lanes.mir26 ; CHECK-NEXT: %3.sub3:sgpr_128 = COPY %2.sub3
348 %3.sub1:sgpr_128 = COPY %1.sub3
350 %3.sub3:sgpr_128 = COPY %2.sub3
427 %43.sub3:vreg_128 = COPY %43.sub1
430 %42.sub3:vreg_128 = COPY %43.sub1
433 %41.sub3:vreg_128 = COPY %43.sub1
436 %40.sub3:vreg_128 = COPY %43.sub1
439 %38.sub3:vreg_128 = COPY %43.sub1
442 %37.sub3:vreg_128 = COPY %43.sub1
517 %9.sub3:vreg_128 = COPY %43.sub1
[all …]
H A Ddetect-dead-lanes.mir51 # CHECK: S_NOP 0, implicit %1.sub3
96 S_NOP 0, implicit %1.sub3
105 S_NOP 0, implicit %4.sub3
130 # CHECK: S_NOP 0, implicit %3.sub3
145 # CHECK: S_NOP 0, implicit %12.sub3
179 S_NOP 0, implicit %3.sub3
194 S_NOP 0, implicit %12.sub3
304 S_NOP 0, implicit %4.sub3
326 # CHECK: S_NOP 0, implicit %6.sub3
356 S_NOP 0, implicit %6.sub3
[all …]
H A Dschedule-barrier.mir16 ; CHECK-NEXT: undef %0.sub3:vreg_128 = COPY $vgpr9
22 ; CHECK-NEXT: undef %4.sub3:vreg_128 = COPY $vgpr5
29 ; CHECK-NEXT: %9.sub3:sgpr_128 = V_READFIRSTLANE_B32 %4.sub3, implicit $exec
35 ; CHECK-NEXT: %12.sub3:sgpr_128 = V_READFIRSTLANE_B32 %0.sub3, implicit $exec
42 undef %43.sub3:vreg_128 = COPY $vgpr9
46 undef %46.sub3:vreg_128 = COPY $vgpr5
58 %33.sub3:sgpr_128 = V_READFIRSTLANE_B32 %46.sub3, implicit $exec
65 %27.sub3:sgpr_128 = V_READFIRSTLANE_B32 %43.sub3, implicit $exec
H A Dexpand-si-indirect.mir46 …ub0, killed %6, %subreg.sub1, killed %7, %subreg.sub2, killed %8, %subreg.sub3, killed %9, %subreg…
55 …led %29, %subreg.sub0, killed %28, %subreg.sub1, killed %27, %subreg.sub2, killed %26, %subreg.sub3
61 …led %34, %subreg.sub0, killed %33, %subreg.sub1, killed %32, %subreg.sub2, killed %31, %subreg.sub3
67 …led %39, %subreg.sub0, killed %38, %subreg.sub1, killed %37, %subreg.sub2, killed %36, %subreg.sub3
69 %41:vgpr_32 = COPY %23.sub3
73 …led %44, %subreg.sub0, killed %43, %subreg.sub1, killed %42, %subreg.sub2, killed %41, %subreg.sub3
79 …led %49, %subreg.sub0, killed %48, %subreg.sub1, killed %47, %subreg.sub2, killed %46, %subreg.sub3
85 …led %54, %subreg.sub0, killed %53, %subreg.sub1, killed %52, %subreg.sub2, killed %51, %subreg.sub3
91 …led %59, %subreg.sub0, killed %58, %subreg.sub1, killed %57, %subreg.sub2, killed %56, %subreg.sub3
93 %61:vgpr_32 = COPY %25.sub3
[all …]
H A Dmerge-image-load-gfx11.mir15 %4:vgpr_32 = COPY %2.sub3
33 %4:vgpr_32 = COPY %2.sub3
52 %4:vgpr_32 = COPY %2.sub3
71 %4:vgpr_32 = COPY %2.sub3
90 %4:vgpr_32 = COPY %2.sub3
109 %4:vgpr_32 = COPY %2.sub3
126 %4:vgpr_32 = COPY %2.sub3
167 %4:vgpr_32 = COPY %2.sub3
185 %4:vgpr_32 = COPY %2.sub3
203 %4:vgpr_32 = COPY %2.sub3
[all …]
H A Dmerge-image-sample.mir15 %4:vgpr_32 = COPY %2.sub3
34 %4:vgpr_32 = COPY %2.sub3
53 %4:vgpr_32 = COPY %2.sub3
72 %4:vgpr_32 = COPY %2.sub3
91 %4:vgpr_32 = COPY %2.sub3
110 %4:vgpr_32 = COPY %2.sub3
127 %4:vgpr_32 = COPY %2.sub3
168 %4:vgpr_32 = COPY %2.sub3
186 %4:vgpr_32 = COPY %2.sub3
204 %4:vgpr_32 = COPY %2.sub3
[all …]
H A Dmubuf-legalize-operands.mir27 # W64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
53 # W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
85 … %6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
104 # W64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
130 # W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
162 … %6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
181 # W64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
207 # W32: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
252 # ADDR64: %18:sgpr_128 = REG_SEQUENCE %15, %subreg.sub0_sub1, %16, %subreg.sub2, %17, %subreg.sub3
295 # W64-NO-ADDR64: [[SRSRC3:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub3, implicit $exec
[all …]
H A Dmerge-image-sample-gfx11.mir15 %4:vgpr_32 = COPY %2.sub3
33 %4:vgpr_32 = COPY %2.sub3
52 %4:vgpr_32 = COPY %2.sub3
71 %4:vgpr_32 = COPY %2.sub3
90 %4:vgpr_32 = COPY %2.sub3
109 %4:vgpr_32 = COPY %2.sub3
126 %4:vgpr_32 = COPY %2.sub3
167 %4:vgpr_32 = COPY %2.sub3
185 %4:vgpr_32 = COPY %2.sub3
203 %4:vgpr_32 = COPY %2.sub3
[all …]
H A Dsched-assert-dead-def-subreg-use-other-subreg.mir24 ; CHECK-NEXT: undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec
32 …; CHECK-NEXT: BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, …
40 ; CHECK-NEXT: %11.sub3:vreg_512 = COPY [[COPY]].sub3
50 undef %0.sub3:vreg_512 = V_MOV_B32_e32 0, implicit $exec
57 …BUFFER_STORE_DWORD_OFFEN %0.sub3, undef %5:vgpr_32, $sgpr24_sgpr25_sgpr26_sgpr27, $sgpr32, 0, 0, 0…
67 %11.sub3:vreg_512 = COPY %4.sub3
H A Dmerge-image-load-gfx10.mir15 %4:vgpr_32 = COPY %2.sub3
33 %4:vgpr_32 = COPY %2.sub3
52 %4:vgpr_32 = COPY %2.sub3
71 %4:vgpr_32 = COPY %2.sub3
90 %4:vgpr_32 = COPY %2.sub3
109 %4:vgpr_32 = COPY %2.sub3
126 %4:vgpr_32 = COPY %2.sub3
167 %4:vgpr_32 = COPY %2.sub3
185 %4:vgpr_32 = COPY %2.sub3
203 %4:vgpr_32 = COPY %2.sub3
[all …]
H A Dmerge-image-load.mir15 %4:vgpr_32 = COPY %2.sub3
34 %4:vgpr_32 = COPY %2.sub3
53 %4:vgpr_32 = COPY %2.sub3
72 %4:vgpr_32 = COPY %2.sub3
91 %4:vgpr_32 = COPY %2.sub3
110 %4:vgpr_32 = COPY %2.sub3
127 %4:vgpr_32 = COPY %2.sub3
168 %4:vgpr_32 = COPY %2.sub3
186 %4:vgpr_32 = COPY %2.sub3
204 %4:vgpr_32 = COPY %2.sub3
[all …]
H A Dmerge-image-sample-gfx10.mir15 %4:vgpr_32 = COPY %2.sub3
33 %4:vgpr_32 = COPY %2.sub3
52 %4:vgpr_32 = COPY %2.sub3
71 %4:vgpr_32 = COPY %2.sub3
90 %4:vgpr_32 = COPY %2.sub3
109 %4:vgpr_32 = COPY %2.sub3
126 %4:vgpr_32 = COPY %2.sub3
167 %4:vgpr_32 = COPY %2.sub3
185 %4:vgpr_32 = COPY %2.sub3
203 %4:vgpr_32 = COPY %2.sub3
[all …]
H A Dmerge-tbuffer.mir29 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %7.sub3
138 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %17.sub3
175 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %17.sub3
212 # GFX9: %{{[0-9]+}}:vgpr_32 = COPY killed %17.sub3
845 # GFX10: %{{[0-9]+}}:vgpr_32 = COPY killed %7.sub3
954 # GFX10: %{{[0-9]+}}:vgpr_32 = COPY killed %17.sub3
991 # GFX10: %{{[0-9]+}}:vgpr_32 = COPY killed %17.sub3
1028 # GFX10: %{{[0-9]+}}:vgpr_32 = COPY killed %17.sub3
1642 # GFX11: %{{[0-9]+}}:vgpr_32 = COPY killed %7.sub3
1751 # GFX11: %{{[0-9]+}}:vgpr_32 = COPY killed %17.sub3
[all …]
H A Dgreedy-liverange-priority.mir26 %27.sub3:vreg_128 = COPY %27.sub0
30 %16.sub3:sgpr_256 = COPY %16.sub0
42 %30.sub3:vreg_128 = COPY %30.sub1
70 %25.sub3:sgpr_256 = COPY %25.sub0
92 %25.sub3:sgpr_256 = COPY %25.sub0
96 %28.sub3:vreg_128 = COPY %28.sub0
H A Dcouldnt-join-subrange-3.mir25 ; GCN-NEXT: %11.sub3:vreg_128 = COPY %11.sub0
32 …; GCN-NEXT: %11.sub3:vreg_128 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, [[COPY]].sub3, im…
47 …; GCN-NEXT: dead %16:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN [[COPY]].sub3, undef %17:sgpr_128,…
77 %52.sub3:vreg_128 = COPY %51
87 %57:vgpr_32 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, %53.sub3, implicit $exec
89 %55.sub3:vreg_128 = COPY killed %57
103 …dead %22:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %53.sub3, undef %24:sgpr_128, 0, 0, 0, 0,…
H A Dsplitkit.mir22 S_NOP 0, implicit-def %0.sub3 : sgpr_128
28 S_NOP 0, implicit %0.sub3
30 S_NOP 0, implicit %0.sub3
79 S_NOP 0, implicit-def %0.sub3 : sgpr_128
102 S_NOP 0, implicit %0.sub3
104 S_NOP 0, implicit %0.sub3
/llvm-project-15.0.7/flang/test/Semantics/
H A Dassign09.f9033 call sub3(float)
42 call sub3(sqrt)
51 call sub3(noInterfaceExternal)
65 subroutine sub3(p) subroutine
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/
H A Dminloop.ll106 %sub3 = sub i32 %blockSize, %blkCnt.020
108 %spec.select14 = select i1 %cmp2, i32 %sub3, i32 %outIndex.019
113 %sub3.1 = sub i32 %blockSize, %blkCnt.0
115 %spec.select14.1 = select i1 %cmp2.1, i32 %sub3.1, i32 %spec.select14
120 %sub3.2 = sub i32 %blockSize, %blkCnt.0.1
122 %spec.select14.2 = select i1 %cmp2.2, i32 %sub3.2, i32 %spec.select14.1
127 %sub3.3 = sub i32 %blockSize, %blkCnt.0.2
129 %spec.select14.3 = select i1 %cmp2.3, i32 %sub3.3, i32 %spec.select14.2
149 %sub3.epil = sub i32 %blockSize, %blkCnt.020.unr
167 %sub3.epil.1 = sub i32 %blockSize, %blkCnt.0.epil
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dllvm.amdgcn.s.buffer.load.ll2705 ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
2751 ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
2797 ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
2847 ; GFX6-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
2891 ; GFX7-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
2935 ; GFX8-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
2990 ; GFX6-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
3038 ; GFX7-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
3086 ; GFX8-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
3137 ; GFX6-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
[all …]
H A Dllvm.amdgcn.raw.tbuffer.store.f16.ll15 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
29 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
48 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
66 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
114 … [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
146 ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
196 ; PACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
252 ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
305 ; PACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
365 ; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
[all …]
H A Dllvm.amdgcn.raw.buffer.store.format.f16.ll14 …E [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
28 …E [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
47 …E [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
60 …E [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
78 …E [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
96 …E [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
136 …E [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3
178 ; UNPACKED-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
230 ; PACKED-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
491 ; UNPACKED-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
[all …]
H A Dllvm.amdgcn.raw.buffer.atomic.fadd.ll16 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
30 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
49 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
63 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
83 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
96 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
115 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
161 ; GFX908-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
216 ; GFX90A-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
275 ; GFX908-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
[all …]
H A Dllvm.amdgcn.raw.tbuffer.store.i8.ll15 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
29 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
50 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
61 ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
100 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
111 ; PACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
167 ; UNPACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
209 … [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3
220 ; PACKED-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
280 ; UNPACKED-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub3
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dmachine-outliner-return-1.ll16 %sub3 = sub nsw i32 %c, %d
17 %mul4 = mul nsw i32 %add2, %sub3
40 %sub3 = sub nsw i32 %c, %d
41 %mul4 = mul nsw i32 %add2, %sub3

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