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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsplitkit-copy-live-lanes.mir346 %2.sub1:sgpr_128 = COPY %1.sub1
429 %42.sub1:vreg_128 = COPY %43.sub1
432 %41.sub1:vreg_128 = COPY %43.sub1
435 %40.sub1:vreg_128 = COPY %43.sub1
438 %38.sub1:vreg_128 = COPY %43.sub1
441 %37.sub1:vreg_128 = COPY %43.sub1
444 %36.sub1:vreg_128 = COPY %43.sub1
447 %35.sub1:vreg_128 = COPY %43.sub1
450 %33.sub1:vreg_128 = COPY %43.sub1
516 %9.sub1:vreg_128 = COPY %43.sub1
[all …]
H A Dpr51516.mir33 %12.sub1:vreg_128 = V_ASHRREV_I32_e32 31, %11.sub2, implicit $exec
41 %16.sub1:vreg_128 = V_ASHRREV_I32_e32 31, %9.sub2, implicit $exec
43 %17.sub1:vreg_128 = V_ASHRREV_I32_e32 31, %9.sub0, implicit $exec
65 %27.sub2:vreg_128 = COPY %4.sub1
71 %25.sub2:vreg_128 = COPY %5.sub1
77 %23.sub2:vreg_128 = COPY %6.sub1
83 %21.sub2:vreg_128 = COPY %7.sub1
89 %19.sub2:vreg_128 = COPY %8.sub1
95 %17.sub2:vreg_128 = COPY %9.sub1
101 %15.sub2:vreg_128 = COPY %10.sub1
[all …]
H A Drename-independent-subregs.mir14 # CHECK: S_NOP 0, implicit %2.sub1
16 # CHECK: S_NOP 0, implicit %1.sub1
17 # CHECK: S_NOP 0, implicit-def %0.sub1
25 S_NOP 0, implicit-def %0.sub1
26 S_NOP 0, implicit %0.sub1
27 S_NOP 0, implicit-def %0.sub1
28 S_NOP 0, implicit %0.sub1
29 S_NOP 0, implicit-def %0.sub1
58 S_NOP 0, implicit-def %0.sub1
64 S_NOP 0, implicit %1.sub1
[all …]
H A Dregcoalesce-cannot-join-failures.mir47 ; CHECK-NEXT: S_ENDPGM 0, implicit %0.sub1
50 %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
51 S_ENDPGM 0, implicit %1.sub1:sreg_64
71 undef %0.sub1:sreg_64 = S_MOV_B32 -1
77 S_ENDPGM 0, implicit %1.sub1:sreg_64
89 ; CHECK-NEXT: S_NOP 0, implicit %0.sub1
94 %0.sub1:sreg_64_xexec = S_MOV_B32 0
95 S_NOP 0, implicit %0.sub1
112 ; CHECK-NEXT: S_NOP 0, implicit %0.sub1
119 %0.sub1:sreg_64_xexec = COPY %0.sub0
[all …]
H A Dcoalesce-identity-copies-undef-subregs.mir32 …; CHECK-NEXT: undef %0.sub1:vreg_64 = nofpexcept V_CEIL_F32_e32 %0.sub1, implicit $mode, implici…
47 undef %0.sub1:vreg_64 = nofpexcept V_CEIL_F32_e32 killed %0.sub1, implicit $mode, implicit $exec
91 undef %0.sub1:vreg_64 = nofpexcept V_CEIL_F32_e32 killed %0.sub1, implicit $mode, implicit $exec
132 … undef %0.sub1:vreg_64 = nofpexcept V_MUL_F32_e32 0, killed %0.sub1, implicit $mode, implicit $exec
157 …; CHECK-NEXT: %0.sub1:vreg_64 = nofpexcept V_MUL_F32_e32 0, %0.sub1, implicit $mode, implicit $e…
173 %0.sub1:vreg_64 = nofpexcept V_MUL_F32_e32 0, killed %0.sub1, implicit $mode, implicit $exec
215 undef %0.sub1:vreg_64 = nofpexcept V_CEIL_F32_e32 killed %0.sub1, implicit $mode, implicit $exec
283 S_NOP 0, implicit %0.sub1
324 undef %2.sub1:vreg_64 = COPY %0.sub1
365 undef %0.sub1:vreg_64 = COPY %0.sub1
[all …]
H A Dcombine-sreg64-inits.mir14 %0.sub1:sgpr_64 = S_MOV_B32 2
24 undef %0.sub1:sgpr_64 = S_MOV_B32 2
41 %1.sub1:sgpr_64 = S_MOV_B32 2
56 %1.sub1:sgpr_64 = S_MOV_B32 2
70 %1.sub1:sgpr_64 = S_MOV_B32 2
89 %0.sub1:sgpr_64 = S_MOV_B32 2
101 %0.sub1:sgpr_64 = S_MOV_B32 2
102 %0.sub1:sgpr_64 = S_MOV_B32 3
114 %0.sub1:sgpr_64 = S_MOV_B32 2
137 %0.sub1:sgpr_64 = S_MOV_B32 2
[all …]
H A Dpromote-constOffset-to-imm.mir21 %9:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, %8, %subreg.sub1
24 %12:sgpr_32 = COPY %1.sub1
29 %19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
36 %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
41 %37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1
77 %12:sgpr_32 = COPY %1.sub1
130 %12:sgpr_32 = COPY %1.sub1
175 %12:sgpr_32 = COPY %1.sub1
195 # GFX9: GLOBAL_STORE_DWORD %{{[0-9]+}}, %0.sub1, 0, 0,
206 %6:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %4, %subreg.sub1
[all …]
H A Dpromote-constOffset-to-imm-gfx10.mir21 %9:vreg_64 = REG_SEQUENCE killed %7, %subreg.sub0, %8, %subreg.sub1
24 %12:sgpr_32 = COPY %1.sub1
29 %19:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
36 %30:vreg_64 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
41 %37:vreg_64 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1
77 %12:sgpr_32 = COPY %1.sub1
134 %12:sgpr_32 = COPY %1.sub1
179 %12:sgpr_32 = COPY %1.sub1
199 # GFX10: GLOBAL_STORE_DWORD %{{[0-9]+}}, %0.sub1, 0, 0
210 %6:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %4, %subreg.sub1
[all …]
H A Dpromote-constOffset-to-imm-gfx90a.mir28 %9:vreg_64_align2 = REG_SEQUENCE killed %7, %subreg.sub0, %8, %subreg.sub1
31 %12:sgpr_32 = COPY %1.sub1
36 %19:vreg_64_align2 = REG_SEQUENCE %14, %subreg.sub0, %17, %subreg.sub1
43 %30:vreg_64_align2 = REG_SEQUENCE %26, %subreg.sub0, %28, %subreg.sub1
48 %37:vreg_64_align2 = REG_SEQUENCE %33, %subreg.sub0, %35, %subreg.sub1
84 %12:sgpr_32 = COPY %1.sub1
137 %12:sgpr_32 = COPY %1.sub1
182 %12:sgpr_32 = COPY %1.sub1
202 # GFX9: GLOBAL_STORE_DWORD %{{[0-9]+}}, %0.sub1, 0, 0,
213 %6:vreg_64_align2 = REG_SEQUENCE %2, %subreg.sub0, %4, %subreg.sub1
[all …]
H A Ddetect-dead-lanes.mir11 # CHECK: S_NOP 0, implicit %3.sub1
16 # CHECK: S_NOP 0, implicit %4.sub1
33 S_NOP 0, implicit %3.sub1
38 S_NOP 0, implicit %4.sub1
94 S_NOP 0, implicit %1.sub1
98 S_NOP 0, implicit %2.sub1
103 S_NOP 0, implicit %4.sub1
129 # CHECK: S_NOP 0, implicit %3.sub1
178 S_NOP 0, implicit %3.sub1
200 S_NOP 0, implicit %16.sub1
[all …]
H A Ddpp_combine_gfx11.mir418 %3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted
529 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
554 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
579 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
604 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
631 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
647 # GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1
660 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
662 %5:vreg_64 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub1, %subreg.sub1
683 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
[all …]
H A Dregcoalesce-keep-valid-lanes-implicit-def-bug39602.mir15 ; CHECK-NEXT: undef %0.sub1:sreg_64 = IMPLICIT_DEF
20 ; CHECK-NEXT: dead %0.sub1:sreg_64 = COPY %0.sub0
21 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]].sub1
24 undef %0.sub1:sreg_64 = IMPLICIT_DEF
29 dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
30 S_ENDPGM 0, implicit %1.sub1:sreg_64
49 ; CHECK-NEXT: dead %0.sub1:sreg_64 = COPY %0.sub0
50 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]].sub1
53 undef %0.sub1:sreg_64 = S_MOV_B32 -1
58 dead %0.sub1:sreg_64 = COPY %0.sub0:sreg_64
[all …]
H A Dspill-empty-live-interval.mir10 # CHECK: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
11 # CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $mode, implicit $exec
12 # CHECK-NEXT: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $m…
15 # CHECK: S_NOP 0, implicit %6.sub1
17 # CHECK-NEXT: S_NOP 0, implicit %8.sub1
29 …undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $mode, implicit…
30 undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
31 dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $mode, implicit $exec
34 S_NOP 0, implicit %2.sub1
35 S_NOP 0, implicit %0.sub1
H A Dsdwa-ops.mir31 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
37 %162:vreg_64 = REG_SEQUENCE %163, %subreg.sub0, %164, %subreg.sub1
43 %172:vreg_64 = REG_SEQUENCE %173, %subreg.sub0, %174, %subreg.sub1
79 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
115 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %66, %subreg.sub1
145 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %65, %subreg.sub1
174 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
203 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %23, %subreg.sub1
234 %62:vreg_64 = REG_SEQUENCE %23, %subreg.sub0, %23, %subreg.sub1
265 %62:vreg_64 = REG_SEQUENCE %63, %subreg.sub0, %64, %subreg.sub1
[all …]
H A Dundef-subreg-use-after-coalesce.mir16 ; CHECK-NEXT: dead %0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
19 %0.sub1:vreg_96 = V_MOV_B32_e32 0, implicit $exec
35 ; CHECK-NEXT: S_ENDPGM 0, implicit undef %2.sub1:vreg_64
37 %0.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec
40 S_ENDPGM 0, implicit %2.sub1
52 # %0.sub1:vreg_128 = V_MOV_B32_e32 0, implicit $exec
54 # S_ENDPGM 0, implicit %1.sub1
69 ; CHECK-NEXT: %2.sub1:vreg_96 = COPY $vgpr1
71 ; CHECK-NEXT: S_NOP 0, implicit %2.sub1
76 %2.sub1:vreg_96 = COPY killed %1
[all …]
H A Drename-independent-subregs-mac-operands.mir58 %13.sub1 = COPY %8
66 %14 = COPY %1.sub1
69 %15.sub1 = COPY killed %14
80 # GCN: undef %8.sub1:vreg_128 = nofpexcept V_MAC_F32_e32 undef %2:vgpr_32, undef %1:vgpr_32, undef …
86 # GCN: %8.sub1:vreg_128 = nofpexcept V_ADD_F32_e32 %8.sub1, %8.sub1, implicit $mode, implicit $exec
90 # GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0,
120 …undef %6.sub1 = nofpexcept V_MAC_F32_e32 undef %2, undef %1, undef %6.sub1, implicit $mode, implic…
131 %6.sub1 = nofpexcept V_ADD_F32_e32 %6.sub1, %6.sub1, implicit $mode, implicit $exec
137 … BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, implicit $exec
147 # GCN-NEXT: dead undef %3.sub1:vreg_128 = COPY %2.sub0
[all …]
H A Dschedule-barrier.mir18 ; CHECK-NEXT: undef %2.sub1:vreg_128 = COPY $vgpr7
19 ; CHECK-NEXT: undef %8.sub1:vreg_64 = COPY $vgpr1
24 ; CHECK-NEXT: undef %6.sub1:vreg_128 = COPY $vgpr3
27 ; CHECK-NEXT: %9.sub1:sgpr_128 = V_READFIRSTLANE_B32 %6.sub1, implicit $exec
33 ; CHECK-NEXT: %12.sub1:sgpr_128 = V_READFIRSTLANE_B32 %2.sub1, implicit $exec
44 undef %41.sub1:vreg_128 = COPY $vgpr7
48 undef %44.sub1:vreg_128 = COPY $vgpr3
50 undef %38.sub1:vreg_64 = COPY $vgpr1
56 %33.sub1:sgpr_128 = V_READFIRSTLANE_B32 %44.sub1, implicit $exec
63 %27.sub1:sgpr_128 = V_READFIRSTLANE_B32 %41.sub1, implicit $exec
H A Ddpp_combine.mir530 %3:vreg_64 = INSERT_SUBREG %0, %2, %subreg.sub1 ; %3.sub1 is inserted
641 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
652 # GCN: %4:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
666 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
691 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
716 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 1, 1, 1, implicit $exec
743 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
759 # GCN: %6:vreg_64 = REG_SEQUENCE %5.sub0, %subreg.sub0, %5.sub1, %subreg.sub1
772 %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
774 %5:vreg_64 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub1, %subreg.sub1
[all …]
H A Dmubuf-legalize-operands.mir23 # W64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
24 # W64: [[STMP0:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[SRSRC0]], %subreg.sub0, [[SRSRC1]], %subreg.sub1
49 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
100 # W64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
126 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
177 # W64: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
203 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
254 # ADDR64: %10:vgpr_32, dead %13:sreg_64_xexec = V_ADDC_U32_e64 %14.sub1, %4.sub1, killed %12, 0, im…
255 # ADDR64: %11:vreg_64 = REG_SEQUENCE %9, %subreg.sub0, %10, %subreg.sub1
315 # W32: [[SRSRC1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[VRSRC]].sub1, implicit $exec
[all …]
H A Dpeephole-opt-regseq-removal.mir8 # %4 -> %3.sub0 -> %2.sub1 -> %1
9 # %5 -> %3.sub1 -> %2.sub0 -> %0
24 …XT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
25 …[0-9]+]]:vreg_64 = REG_SEQUENCE [[REG_SEQUENCE]].sub1, %subreg.sub0, [[REG_SEQUENCE]].sub0, %subre…
31 %2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
32 %3:vreg_64 = REG_SEQUENCE %2.sub1, %subreg.sub0, %2.sub0, %subreg.sub1
34 %5:vgpr_32 = COPY %3.sub1
H A Dsubreg-undef-def-with-other-subreg-defs.mir8 # current vreg uses because it shared no lanes with %0.sub1 use on the
24 ; CHECK-NEXT: %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
34 ; CHECK-NEXT: S_NOP 0, implicit %0.sub1
39 %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
46 INLINEASM &"", 1, 851978, def undef %0.sub0, 851978, def %0.sub1
47 S_NOP 0, implicit %0.sub1
65 ; CHECK-NEXT: %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
75 ; CHECK-NEXT: S_NOP 0, implicit %0.sub1
80 %0.sub1:vreg_64 = V_MOV_B32_e32 0, implicit $exec
87 INLINEASM &"", 1, 851978, def %0.sub1, 851978, def undef %0.sub0
[all …]
/llvm-project-15.0.7/lldb/test/API/macosx/duplicate-archive-members/
H A DMakefile6 libfoo.a: a.c sub1/a.c
8 mkdir -p sub1
9 $(CC) $(CFLAGS) -c $(<D)/sub1/a.c -o sub1/a.o
11 touch -t '198001010000.01' sub1/a.o
12 $(AR) $(ARFLAGS) $@ a.o sub1/a.o
13 rm a.o sub1/a.o
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-reg-sequence.mir22 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
37 …-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1
38 %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $sgpr1, %subreg.sub1
58 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
73 …-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
74 %0:_(s64) = REG_SEQUENCE $sgpr0, %subreg.sub0, $vgpr0, %subreg.sub1
94 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
109 …-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1
110 %0:_(s64) = REG_SEQUENCE $vgpr0, %subreg.sub0, $sgpr0, %subreg.sub1
130 %2:_(s64) = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
[all …]
H A Dinst-select-constant.mir211 …QUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
215 …ENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_MOV_B32_3]], %subreg.sub1
218 …ENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_4]], %subreg.sub0, [[S_MOV_B32_5]], %subreg.sub1
221 …ENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_6]], %subreg.sub0, [[S_MOV_B32_7]], %subreg.sub1
229 …QUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
233 …ENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_2]], %subreg.sub0, [[S_MOV_B32_3]], %subreg.sub1
236 …ENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_4]], %subreg.sub0, [[S_MOV_B32_5]], %subreg.sub1
350 …QUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
368 …QUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
476 …QUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_1]], %subreg.sub1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dusub-overflow-known-by-implied-cond.ll23 %r1 = extractvalue { i32, i1 } %sub1, 0
24 %c1 = extractvalue { i32, i1 } %sub1, 1
51 %r1 = extractvalue { i32, i1 } %sub1, 0
52 %c1 = extractvalue { i32, i1 } %sub1, 1
79 %r1 = extractvalue { i32, i1 } %sub1, 0
80 %c1 = extractvalue { i32, i1 } %sub1, 1
107 %r1 = extractvalue { i32, i1 } %sub1, 0
108 %c1 = extractvalue { i32, i1 } %sub1, 1
136 %r1 = extractvalue { i32, i1 } %sub1, 0
137 %c1 = extractvalue { i32, i1 } %sub1, 1
[all …]

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