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/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp339 for (unsigned su = 0, e = DAG->SUnits.size(); su != e; ++su) { in apply() local
341 if (DAG->SUnits[su].getInstr()->isCall()) in apply()
342 LastSequentialCall = &DAG->SUnits[su]; in apply()
344 else if (DAG->SUnits[su].getInstr()->isCompare() && LastSequentialCall) in apply()
345 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier)); in apply()
347 else if (SchedPredsCloser && LastSequentialCall && su > 1 && su < e-1 && in apply()
348 shouldTFRICallBind(HII, DAG->SUnits[su], DAG->SUnits[su+1])) in apply()
349 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); in apply()
365 const MachineInstr *MI = DAG->SUnits[su].getInstr(); in apply()
378 LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su]; in apply()
[all …]
/llvm-project-15.0.7/compiler-rt/lib/asan/scripts/
H A Dasan_device_setup41 $ADB shell su -c "rm \\\"$2/$FILENAME\\\"" >&/dev/null
42 $ADB shell su -c "cat \\\"/data/local/tmp/$FILENAME\\\" > \\\"$2/$FILENAME\\\""
43 $ADB shell su -c "rm \\\"/data/local/tmp/$FILENAME\\\""
54 $ADB shell su -c "mount -o rw,remount $STORAGE /system"
65 $ADB shell su -c "$*"
85 …$ADB shell su -c "[ -f \\\"$1\\\" ] && cat \\\"$1\\\" > \\\"/data/local/tmp/$FILENAME\\\" && chown…
140 --use-su)
157 SU_TEST_OUT=`$ADB shell su -c "echo foo" 2>&1 | sed 's/\r$//'`
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-dagcombiner-dead-indexed-load.ll18 define void @test(%"struct.SU"* nocapture %su) {
20 %r1 = getelementptr inbounds %"struct.SU", %"struct.SU"* %su, i64 1, i32 5
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Dcasted-argument.ll19 %su = sub i32 0, %cp ; <i32> [#uses=1]
20 %ge = getelementptr i8, i8* %pn, i32 %su ; <i8*> [#uses=2]
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h81 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} in PhysRegSUOper()
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td423 // mod_[su].[bhwd], div_[su].[bhwd]
427 // hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd],
428 // maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd],
568 // copy.[su]_[bhwd]
H A DMipsScheduleGeneric.td1543 // mod_[su].[bhwd], div_[su].[bhwd]
1547 // hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd],
1548 // maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd],
1598 // copy.[su]_[bhwd]
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DScheduleDAGInstrs.cpp98 for (const SUnit *su : L) { in dumpSUList() local
99 dbgs() << "SU(" << su->NodeNum << ")"; in dumpSUList()
100 if (su != L.back()) in dumpSUList()
/llvm-project-15.0.7/llvm/include/llvm/Target/GlobalISel/
H A DCombine.td360 // Transform d = [su]div(x, y) and r = [su]rem(x, y) - > d, r = [su]divrem(x, y)
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td166 def SU : BinaryRX<"su", 0x7F, null_frag, FP32, load, 4>;
/llvm-project-15.0.7/llvm/
H A DCREDITS.TXT420 E: [email protected].su
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARM.td132 // True if subtarget supports [su]div in Thumb mode.
137 // True if subtarget supports [su]div in ARM mode.
H A DARMScheduleA57.td1115 "VQRSHRN", "VQRSHRUN", "VQSHL(si|ui|su)", "VQSHRN", "VQSHRUN", "VRSHR(s|u)",
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td161 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
164 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
167 def SDTFPToIntSatOp : SDTypeProfile<1, 2, [ // fp_to_[su]int_sat
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td786 // XXX: Lowering SELECT_CC will sometimes generate fp_to_[su]int nodes,
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dcast-int-icmp-eq-0.ll656 ; icmp (bitcast ([su]itofp X)), Y -> icmp X, Y
/llvm-project-15.0.7/llvm/test/MC/SystemZ/
H A Dinsn-good.s15877 #CHECK: su %f0, 0 # encoding: [0x7f,0x00,0x00,0x00]
15878 #CHECK: su %f0, 4095 # encoding: [0x7f,0x00,0x0f,0xff]
15879 #CHECK: su %f0, 0(%r1) # encoding: [0x7f,0x00,0x10,0x00]
15880 #CHECK: su %f0, 0(%r15) # encoding: [0x7f,0x00,0xf0,0x00]
15885 su %f0, 0
15886 su %f0, 4095
15887 su %f0, 0(%r1)
15888 su %f0, 0(%r15)
15889 su %f0, 4095(%r1,%r15)
15890 su %f0, 4095(%r15,%r1)
[all …]
H A Dinsn-bad.s6998 #CHECK: su %f0, -1
7000 #CHECK: su %f0, 4096
7002 su %f0, -1
7003 su %f0, 4096
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsARM.td517 // use a "su" suffix.
/llvm-project-15.0.7/llvm/test/MC/Disassembler/SystemZ/
H A Dinsns.txt17391 # CHECK: su %f0, 0
17394 # CHECK: su %f0, 4095
17397 # CHECK: su %f0, 0(%r1)
17400 # CHECK: su %f0, 0(%r15)
17403 # CHECK: su %f0, 4095(%r1,%r15)
17406 # CHECK: su %f0, 4095(%r15,%r1)
17409 # CHECK: su %f15, 0
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.td3978 // These instructions saturate like fp_to_[su]int_sat.
6083 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
6088 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
8238 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
/llvm-project-15.0.7/clang/docs/
H A DClangCommandLineReference.rst2519 Emit .su file containing information on function stack sizes
/llvm-project-15.0.7/clang/include/clang/Driver/
H A DOptions.td3027 HelpText<"Emit .su file containing information on function stack sizes">;