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/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dinlineasm-64bit.ll7 ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
16 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
17 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
18 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
19 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
20 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
21 ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
37 …ect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, …
39 …ect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, …
40 …ect " strexd $1, ${1:H}, [$0]\0A strexd $2, ${2:H}, [$0]\0A strexd $3, ${3:H}, [$0]\0A strexd $4, …
[all …]
H A Datomic-64bit.ll16 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
28 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
47 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
59 ; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
78 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
109 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
140 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
228 ; CHECK-NOT: strexd
230 ; CHECK-NOT: strexd
235 ; CHECK-THUMB-NOT: strexd
[all …]
H A DPR15053.ll4 declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
11 %2 = tail call i32 @llvm.arm.strexd(i32 %1, i32 undef, i8* undef) nounwind
H A Dldstrex-m.ll14 ; CHECK-NOT: strexd
23 ; CHECK-NOT: strexd
H A Dldstrex.ll23 ; CHECK: strexd
29 %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr)
30 ret i32 %strexd
34 declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
H A Dcmpxchg-O0.ll89 ; CHECK: strexd [[STATUS:[lr0-9]+]], r8, r9, [r1]
108 ; CHECK: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [[[ADDR]]]
124 ; CHECK: strexd
H A Datomic-load-store.ll318 ; ARM-NEXT: strexd r1, r2, r3, [r0]
361 ; ARMOPTNONE-NEXT: strexd r0, r10, r11, [r3]
388 ; THUMBTWO-NEXT: strexd r3, r1, r2, [r0]
422 ; ARMV6-NEXT: strexd r1, r2, r3, [r0]
H A Datomic-ops-v8.ll96 ; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
288 ; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
480 ; CHECK: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]]
569 ; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]]
794 ; CHECK-ARM: strexd [[STATUS:r[0-9]+]], [[MINLO]], [[MINHI]], [r[[ADDR]]]
795 ; CHECK-THUMB: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r[[ADDR]]]
1157 ; CHECK: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]]
H A Datomicrmw_exclusive_monitor_ints.ll6801 ; CHECK-ARM8-NEXT: strexd r0, r8, r9, [r3]
6857 ; CHECK-ARM6-NEXT: strexd r0, r8, r9, [r3]
7011 ; CHECK-ARM8-NEXT: strexd r0, r8, r9, [r3]
7067 ; CHECK-ARM6-NEXT: strexd r0, r8, r9, [r3]
7221 ; CHECK-ARM8-NEXT: strexd r0, r8, r9, [r3]
7277 ; CHECK-ARM6-NEXT: strexd r0, r8, r9, [r3]
7431 ; CHECK-ARM8-NEXT: strexd r0, r8, r9, [r3]
7487 ; CHECK-ARM6-NEXT: strexd r0, r8, r9, [r3]
7643 ; CHECK-ARM8-NEXT: strexd r0, r8, r9, [r3]
7701 ; CHECK-ARM6-NEXT: strexd r0, r8, r9, [r3]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Darm-STREXD-reencoding.txt9 # CHECK: strexd r1, r2, r3, [r0] @ encoding: [0x92,0x1f,0xa0,0xe1]
10 # CHECK: strexd r4, r0, r1, [r3] @ encoding: [0x90,0x4f,0xa3,0xe1]
11 # CHECK: strexd sp, r2, r3, [r4] @ encoding: [0x92,0xdf,0xa4,0xe1]
12 # CHECK: strexd r10, r0, r1, [r6] @ encoding: [0x90,0xaf,0xa6,0xe1]
13 # CHECK: strexd r5, r12, sp, [r8] @ encoding: [0x9c,0x5f,0xa8,0xe1]
H A Dinvalid-thumbv7-xfail.txt5 # Undefined encodings for ldrexd/strexd
35 # FIXME: should be unpredictable since it's "strexd r8, r7, r8, [r2]"
H A Dthumb-tests.txt173 # CHECK: strexd r1, r7, r8, [r2]
H A Dbasic-arm-instructions.txt1944 # CHECK: strexd r6, r2, r3, [r8
1945 # CHECK: strexd sp, r0, r1, [r0]
/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb2-ldrexd-strexd.s8 strexd r3, r4, r5, [r6]
11 @ CHECK: strexd r3, r4, r5, [r6] @ encoding: [0xc6,0xe8,0x73,0x45]
H A Dthumbv8m.s87 strexd r0, r1, r2, [r3] label
H A Ddiagnostics.s328 @ Out of order Rt/Rt2 operands for ldrexd/strexd
330 strexd r6, r5, r3, [r8]
336 @ CHECK-ERRORS: strexd r6, r5, r3, [r8]
H A Dbasic-arm-instructions.s2896 strexd r6, r2, r3, [r8]
2901 @ CHECK: strexd r6, r2, r3, [r8] @ encoding: [0x92,0x6f,0xa8,0xe1]
H A Dbasic-thumb2-instructions.s3143 strexd r9, r3, r6, [r4]
3150 @ CHECK: strexd r9, r3, r6, [r4] @ encoding: [0xc4,0xe8,0x79,0x36]
/llvm-project-15.0.7/compiler-rt/lib/builtins/arm/
H A Dsync-ops.h48 strexd r6, r4, r5, [r12]; \
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-ldxr-stxr.ll27 %strexd = tail call i32 @llvm.aarch64.stxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
28 ret i32 %strexd
204 %strexd = tail call i32 @llvm.aarch64.stlxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
205 ret i32 %strexd
/llvm-project-15.0.7/llvm/test/Transforms/AtomicExpand/ARM/
H A Datomic-expansion-v7.ll114 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
394 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
H A Datomic-expansion-v8.ll245 ; CHECK: [[TRYAGAIN:%.*]] = call i32 @llvm.arm.strexd(i32 [[NEWLO]], i32 [[NEWHI]], i8* [[PTR8]])
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/ARM/
H A Dcortex-a57-basic-instructions.s685 strexd r6, r2, r3, [r8]
686 strexd sp, r0, r1, [r0]
1555 # CHECK-NEXT: 0 0 0.00 * U strexd r6, r2, r3, [r8]
1556 # CHECK-NEXT: 0 0 0.00 * U strexd sp, r0, r1, [r0]
2432 # CHECK-NEXT: - - - - - - - - strexd r6, r2, r3, [r8]
2433 # CHECK-NEXT: - - - - - - - - strexd sp, r0, r1, [r0]
H A Dcortex-a57-thumb.s661 strexd r9, r3, r6, [r4]
1568 # CHECK-NEXT: 0 0 0.00 * U strexd r9, r3, r6, [r4]
2482 # CHECK-NEXT: - - - - - - - - strexd r9, r3, r6, [r4]
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td530 // These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.

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