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/llvm-project-15.0.7/llvm/test/CodeGen/NVPTX/
H A Denvreg.ll5 declare i32 @llvm.nvvm.read.ptx.sreg.envreg0()
6 declare i32 @llvm.nvvm.read.ptx.sreg.envreg1()
7 declare i32 @llvm.nvvm.read.ptx.sreg.envreg2()
8 declare i32 @llvm.nvvm.read.ptx.sreg.envreg3()
9 declare i32 @llvm.nvvm.read.ptx.sreg.envreg4()
10 declare i32 @llvm.nvvm.read.ptx.sreg.envreg5()
11 declare i32 @llvm.nvvm.read.ptx.sreg.envreg6()
12 declare i32 @llvm.nvvm.read.ptx.sreg.envreg7()
13 declare i32 @llvm.nvvm.read.ptx.sreg.envreg8()
14 declare i32 @llvm.nvvm.read.ptx.sreg.envreg9()
[all …]
H A Dintrinsic-old.ll20 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
28 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.y()
36 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.z()
43 %x = call i32 @llvm.nvvm.read.ptx.sreg.tid.w()
285 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
286 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
308 declare i32 @llvm.nvvm.read.ptx.sreg.smid()
321 declare i32 @llvm.nvvm.read.ptx.sreg.pm0()
322 declare i32 @llvm.nvvm.read.ptx.sreg.pm1()
323 declare i32 @llvm.nvvm.read.ptx.sreg.pm2()
[all …]
H A Dintrinsics.ll99 ; Most of nvvm.read.ptx.sreg.* intrinsics always return the same value and may
104 %a = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
106 %b = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
117 %a = tail call i32 @llvm.nvvm.read.ptx.sreg.clock()
119 %b = tail call i32 @llvm.nvvm.read.ptx.sreg.clock()
128 %a = tail call i64 @llvm.nvvm.read.ptx.sreg.clock64()
130 %b = tail call i64 @llvm.nvvm.read.ptx.sreg.clock64()
146 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
147 declare i32 @llvm.nvvm.read.ptx.sreg.clock()
148 declare i64 @llvm.nvvm.read.ptx.sreg.clock64()
/llvm-project-15.0.7/llvm/test/CodeGen/AVR/pseudo/
H A DASRWNRd.mir19 ; CHECK: $r14 = ADDRdRr killed $r14, killed $r14, implicit-def $sreg
21 ; CHECK-NEXT: $r14 = ADCRdRr $r14, $r14, implicit-def $sreg, implicit $sreg
22 ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg
23 $r15r14 = ASRWNRd $r15r14, 7, implicit-def $sreg
27 ; CHECK-NEXT: $r13 = SBCRdRr $r13, $r13, implicit-def $sreg, implicit killed $sreg
28 $r13r12 = ASRWNRd $r13r12, 8, implicit-def $sreg
31 ; CHECK-NEXT: $r10 = SBCRdRr killed $r10, killed $r10, implicit-def $sreg, implicit $sreg
34 ; CHECK-NEXT: $r10 = ADCRdRr $r10, $r10, implicit-def $sreg, implicit killed $sreg
35 $r11r10 = ASRWNRd $r11r10, 14, implicit-def $sreg
38 ; CHECK-NEXT: $r17 = SBCRdRr killed $r17, killed $r17, implicit-def $sreg, implicit killed $sreg
[all …]
H A DLSLWNRd.mir21 ; CHECK-NEXT: $r17 = ANDIRdK killed $r17, 240, implicit-def dead $sreg
22 ; CHECK-NEXT: $r17 = EORRdRr killed $r17, $r16, implicit-def dead $sreg
23 ; CHECK-NEXT: $r16 = ANDIRdK $r16, 240, implicit-def dead $sreg
24 ; CHECK-NEXT: $r17 = EORRdRr $r17, $r16, implicit-def $sreg
25 $r17r16 = LSLWNRd $r17r16, 4, implicit-def $sreg
28 ; CHECK-NEXT: $r18 = EORRdRr $r18, $r18, implicit-def $sreg
29 $r19r18 = LSLWNRd $r19r18, 8, implicit-def $sreg
33 ; CHECK-NEXT: $r21 = ANDIRdK $r21, 240, implicit-def dead $sreg
34 ; CHECK-NEXT: $r20 = EORRdRr $r20, $r20, implicit-def $sreg
35 $r21r20 = LSLWNRd $r21r20, 12, implicit-def $sreg
H A DLSRWNRd.mir21 ; CHECK-NEXT: $r16 = ANDIRdK killed $r16, 15, implicit-def dead $sreg
22 ; CHECK-NEXT: $r16 = EORRdRr killed $r16, $r17, implicit-def dead $sreg
23 ; CHECK-NEXT: $r17 = ANDIRdK $r17, 15, implicit-def dead $sreg
24 ; CHECK-NEXT: $r16 = EORRdRr $r16, $r17, implicit-def $sreg
25 $r17r16 = LSRWNRd $r17r16, 4, implicit-def $sreg
28 ; CHECK-NEXT: $r19 = EORRdRr $r19, $r19, implicit-def $sreg
29 $r19r18 = LSRWNRd $r19r18, 8, implicit-def $sreg
33 ; CHECK-NEXT: $r20 = ANDIRdK $r20, 15, implicit-def dead $sreg
34 ; CHECK-NEXT: $r21 = EORRdRr $r21, $r21, implicit-def $sreg
35 $r21r20 = LSRWNRd $r21r20, 12, implicit-def $sreg
H A DCPCWRdRr.mir17 liveins: $r21r20, $r23r22, $sreg
21 ; CHECK: CPCRdRr $r20, $r22, implicit-def $sreg, implicit killed $sreg
22 ; CHECK-NEXT: CPCRdRr $r21, $r23, implicit-def $sreg, implicit killed $sreg
24 CPCWRdRr $r21r20, $r23r22, implicit-def $sreg, implicit $sreg
H A DSBCIWRdK.mir17 liveins: $r21r20, $sreg
21 ; CHECK: $r20 = SBCIRdK $r20, 175, implicit-def $sreg, implicit killed $sreg
22 ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
24 $r21r20 = SBCIWRdK $r21r20, 64175, implicit-def $sreg, implicit $sreg
H A DADCWRdRr.mir17 liveins: $r15r14, $r21r20, $sreg
21 ; CHECK: $r14 = ADCRdRr $r14, $r20, implicit-def $sreg, implicit $sreg
22 ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
24 $r15r14 = ADCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
H A DLSLBNRd.mir19 ; CHECK: $r17 = RORRd killed $r17, implicit-def $sreg, implicit undef $sreg
20 ; CHECK-NEXT: $r17 = EORRdRr killed $r17, killed $r17, implicit-def $sreg
21 ; CHECK-NEXT: $r17 = RORRd $r17, implicit-def $sreg, implicit killed $sreg
22 $r17 = LSLBNRd $r17, 7, implicit-def $sreg
H A DSBCWRdRr.mir17 liveins: $r15r14, $r21r20, $sreg
21 ; CHECK: $r14 = SBCRdRr $r14, $r20, implicit-def $sreg
22 ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
24 $r15r14 = SBCWRdRr $r15r14, $r21r20, implicit-def $sreg, implicit $sreg
H A DLSRBNRd.mir19 ; CHECK: $r17 = ADCRdRr killed $r17, killed $r17, implicit-def $sreg, implicit undef $sreg
20 ; CHECK-NEXT: $r17 = EORRdRr killed $r17, killed $r17, implicit-def $sreg
21 ; CHECK-NEXT: $r17 = ADCRdRr $r17, $r17, implicit-def $sreg, implicit killed $sreg
22 $r17 = LSRBNRd $r17, 7, implicit-def $sreg
H A DSTDWPtrQRr.mir41 ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
42 ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
50 ; CHECK: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
51 ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
59 ; CHECK-NEXT: $r28 = SUBIRdK killed $r28, 193, implicit-def $sreg
60 ; CHECK-NEXT: $r29 = SBCIRdK killed $r29, 255, implicit-def $sreg, implicit killed $sreg
H A DLSRWRd.mir19 ; CHECK: $r15 = LSRRd $r15, implicit-def $sreg
20 ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
22 $r15r14 = LSRWRd $r15r14, implicit-def $sreg
H A DASRWRd.mir19 ; CHECK: $r15 = ASRRd $r15, implicit-def $sreg
20 ; CHECK-NEXT: $r14 = RORRd $r14, implicit-def $sreg, implicit killed $sreg
22 $r15r14 = ASRWRd $r15r14, implicit-def $sreg
H A DASRBNRd.mir19 ; CHECK: $r17 = ADDRdRr killed $r17, killed $r17, implicit-def $sreg
20 ; CHECK-NEXT: $r17 = SBCRdRr $r17, $r17, implicit-def $sreg, implicit killed $sreg
21 $r17 = ASRBNRd $r17, 7, implicit-def $sreg
H A DLSLWRd.mir19 ; CHECK: $r14 = ADDRdRr $r14, $r14, implicit-def $sreg
20 ; CHECK-NEXT: $r15 = ADCRdRr $r15, $r15, implicit-def $sreg, implicit killed $sreg
22 $r15r14 = LSLWRd $r15r14, implicit-def $sreg
H A DSUBIWRdK.mir21 ; CHECK: $r20 = SUBIRdK $r20, 175, implicit-def $sreg
22 ; CHECK-NEXT: $r21 = SBCIRdK $r21, 250, implicit-def $sreg, implicit killed $sreg
24 $r21r20 = SUBIWRdK $r21r20, 64175, implicit-def $sreg
H A DCPWRdRr.mir21 ; CHECK: CPRdRr $r14, $r20, implicit-def $sreg
22 ; CHECK-NEXT: CPCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
24 CPWRdRr $r15r14, $r21r20, implicit-def $sreg
H A DSUBWRdRr.mir21 ; CHECK: $r14 = SUBRdRr $r14, $r20, implicit-def $sreg
22 ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
24 $r15r14 = SUBWRdRr $r15r14, $r21r20, implicit-def $sreg
H A DSEXT.mir21 ; CHECK-NEXT: $r15 = ADDRdRr killed $r15, killed $r15, implicit-def $sreg
22 ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
24 $r15r14 = SEXT $r31, implicit-def $sreg
H A DADDWRdRr.mir21 ; CHECK: $r14 = ADDRdRr $r14, $r20, implicit-def $sreg
22 ; CHECK-LABEL: $r15 = ADCRdRr $r15, $r21, implicit-def $sreg, implicit killed $sreg
24 $r15r14 = ADDWRdRr $r15r14, $r21r20, implicit-def $sreg
H A DZEXT.mir21 ; CHECK-NEXT: $r15 = ADDRdRr killed $r15, killed $r15, implicit-def $sreg
22 ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
24 $r15r14 = SEXT $r31, implicit-def $sreg
H A DNEGWRd.mir21 ; CHECK: $r15 = NEGRd killed $r15, implicit-def dead $sreg
23 ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r1, implicit-def $sreg, implicit killed $sreg
25 $r15r14 = NEGWRd $r15r14, implicit-def $sreg
/llvm-project-15.0.7/llvm/test/Analysis/DivergenceAnalysis/NVPTX/
H A Ddaorder.ll9 %tid = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
41 declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
42 declare i32 @llvm.nvvm.read.ptx.sreg.tid.y()
43 declare i32 @llvm.nvvm.read.ptx.sreg.tid.z()
44 declare i32 @llvm.nvvm.read.ptx.sreg.laneid()

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